Phase-locked loop circuit

Oscillators – Automatic frequency stabilization using a phase or frequency... – Afc with logic elements

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331 17, 331 25, 331 34, 331 8, 331113R, 331177R, 360 51, 375376, H03L 708, H03L 7085, H03L 7089, H03L 7099

Patent

active

054382998

ABSTRACT:
A PLL circuit comprising a phase comparator unit which forms a differentiation signal based upon both edges of an external signal, outputs an early pulse only during a period in which the differentiation signal is overlapped on a period from the leading edge to the trailing edge of a reference signal, and outputs a late pulse only during a period in which the differentiation signal is overlapped on a period from the trailing edge to the leading edge thereof, a charge pump unit which calculates and compares the amounts of integration of the early pulse and the late pulse, lowers the output voltage when the amount of the late pulse is larger than the amount of the early pulse and raises the output voltage when it is smaller, and a VCO which outputs a corrected reference signal of which the frequency decreases or increases accompanying the increase or decrease in the output voltage of the charge pump unit, wherein the VCO is controlled by the output voltage of the charge pump unit and by the early pulse and the late pulse, and works to raise the oscillation frequency when the late pulse is longer than the early pulse and to lower the oscillation frequency when it is shorter.

REFERENCES:
patent: 5105169 (1992-04-01), Yamazaki et al.
patent: 5164966 (1992-11-01), Hershberger
patent: 5175884 (1992-12-01), Suarez

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