Phase-locked loop architecture for a programmable logic device

Details Phase-locked loop architecture for a programmable logic device Phase-locked loop architecture for a programmable logic device

1998-03-27

1999-12-07

Lam, Tuan T.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

327159, 327292, H03L 706

Patent

active

059990252

ABSTRACT:
A programmable logic device (PLD) which includes a phase comparator in addition to the conventional configurable logic circuitry normally present in the PLD. The configurable logic circuitry of the PLD includes a clock distribution circuit which is configured to route a clock signal VCO.sub.OUT generated by a voltage controlled oscillator (VCO) throughout the PLD as a distributed clock signal (DIST.sub.-- CLK). The DIST.sub.-- CLK signal is used to clock the output registers which route data values out of the PLD. The DIST.sub.-- CLK signal is also provided to the phase comparator. The phase comparator is also coupled to receive a clock signal CLK.sub.IN from an external device. In response, the phase comparator generates an error signal which is representative of the phase difference between the CLK.sub.IN and DIST.sub.-- CLK signals. This error signal is provided to a loop filter. In response, the loop filter generates a control signal, which in turn, controls the frequency of the VCO.sub.OUT signal generated by the VCO. The frequency of the VCO.sub.OUT signal is controlled such that the DIST.sub.-- CLK signal is synchronized with the CLK.sub.IN signal.

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"The Programmable Logic Data Book" published 1994, available from Xilinx, Inc., 2100 Logic Drive, San Jose, California 95124, pp. 2-5 to 2-102.

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