Phase-locked loop apparatus and method

Details Phase-locked loop apparatus and method Phase-locked loop apparatus and method

2001-02-05

2003-04-01

Kinkead, Arnold (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Plural a.f.s. for a single oscillator

C331S00100A, C375S376000, C360S051000

Reexamination Certificate

active

06542039

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a phase-locked loop apparatus and, more particularly, to a phase-locked loop apparatus improved by digitizing a phase-locked loop which is used to reproduce a clock for reproducing digital data recorded on recording media such as optical disk media, magneto-optical disk media, and magnetic media.
BACKGROUND ART
Optical disk apparatuses are widely known as one of apparatuses for recording and reproducing digital data. In the optical disk apparatus, a phase-locked loop (PLL) circuit is conventionally used to lock a phase of a clock component included in a reproduction signal and a phase of a reproduction clock, when the digital data is reproduced. Particularly, an erasable optical disk medium has plural unit blocks called “sectors”, each of which comprises a set of a header part on which address information and the like is written and a data part on which the digital data is actually recorded. The phase locking is performed sector by sector by the phase-locked loop.
In order to perform this intermittent reproduction normally, the header part and data part have locking patterns (VFO patterns)
42
a
-
42
d
, as shown in
FIG. 19
, each of which comprises a single pattern (single frequency). The data reproduction is performed using a method of increasing the response characteristic of the phase-locked loop circuit to perform high-speed and stable phase locking in these VFO pattern areas, and decreasing the response characteristic of the phase-locked loop circuit before ends of the VFO pattern areas to reduce influences of noises and the like, thereby to maintain a locked state.
FIG. 19
is a diagram showing a data format in a sector of an optical disk reproduction apparatus. In the figure, reference numeral
43
designates a sector mark (hereinafter referred to as SM) indicating a start position of the sector. Numeral
44
designates an address mark (hereinafter referred to as AM) indicating a start position of address information. Numeral
45
designates address information (hereinafter referred to as ID) indicating the address of the sector. Numeral
46
designates a postamble (hereinafter referred to as PA) indicating an end point of each of the header part and the data part. Numeral
47
designates a data mark (hereinafter referred to as DM) indicating a start position of data
48
.
FIG. 20
is a block diagram illustrating a digital data reproduction circuit of a prior art optical disk reproduction apparatus.
The prior art optical disk reproduction apparatus as shown in
FIG. 20
is constituted by an optical disk
49
, a reproduction means
50
, a waveform equalization means
1
, a binarization means
51
, a phase-locked loop circuit
52
, a loop gain switching unit
57
, and a demodulation circuit
58
. The phase-locked loop circuit
52
is constituted by a phase comparator
53
, a loop filter
54
, an amplifier
55
, and a Voltage Controlled Oscillator (VCO)
56
.
Hereinafter, its operation will be described.
On the optical disk
49
medium, digital data comprising 0 and 1, the number of continuous 0 or 1 being controlled to from 3 to 14 inclusive, is recorded as in the 8-16 modulation method for example. In a reproduction signal which is obtained by reproducing data with the reproduction means
50
, as the recording density of the data in the linear direction is increased, the amplitude of a waveform having high-band frequency components is attenuated by interference. Then, the waveform equalization means
1
corrects the reproduction signal so as to emphasize its high-band frequency components. The binarization means
51
binarizes the reproduction signal having the emphasized high-band frequency components at a prescribed slice level to convert the signal into a binarized digital signal. In the phase-locked loop circuit
52
, a phase of a reproduction clock as a free running frequency of the phase-locked loop circuit
52
and a phase of a clock component of the binarized signal are compared by the phase comparator
53
, and the phase of the reproduction clock is changed on the basis of phase error information which is output as a result of the comparison so as to have the minimum phase error, by using the loop filter
54
, the amplifier
55
and the VCO
56
, whereby the phase of the clock component of the binarized signal and the phase of the reproduction clock are locked. The response characteristic of the phase-locked loop circuit
52
is switched by the loop gain switching unit
57
. Then, the binarized signal and the locked reproduction clock are input to the demodulation circuit
58
to demodulate the digital data.
In the VFO pattern areas on the recording medium, a range where the reproduction is normally performed is sometimes limited due to defects of the recording medium, servo processing or signal processing in the reproduction of the recording medium. Accordingly, improvements are made to perform the phase locking surely as in a method of detecting the defects or the method as shown in
FIG. 19
of detecting SM
43
, AM
44
, and DM
47
to make the best use of all the VFO pattern areas.
The above-mentioned prior art is adapted to a method which binarizes the reproduction signal to demodulate the digital data. However, when a signal-to-noise ratio of the reproduction signal is significantly deteriorated as the density in,the linear direction is increased, the quality of reproduced data is deteriorated.
Accordingly, as the recording density in the linear direction becomes higher, a PRML (Partial Response Maximum Likelihood) signal processing method as a signal processing method which is suitable for the high-density recording and reproduction in the linear direction is increasingly adopted. The PRML signal processing method is the one which urges intentional waveform interference for the reproduction signal, equalizes the reproduction signal with a band which is controlled to reduce emphasis on noises to the utmost, and thereafter demodulates data by a maximum likelihood decoder for demodulating the most likelihood series in accordance with a known regulation of interference. However, when this PRML signal processing method is utilized, multi-bit data obtained by sampling a reproduction clock which is locked to a phase of a clock component included in the reproduction signal should be generated.
This prior art phase-locked loop circuit is constituted by analog elements. Accordingly, a system where analog circuits and digital circuits are mixed in a complex manner is obtained and this system is not suitable for the integration. In addition, the dispersion of characteristics caused by the analog elements constituting the analog circuits or secular changes occur in the analog circuits. Accordingly, careful consideration should be given also to the quality control, compensation circuits and the like, whereby the cost of the digital data reproduction apparatus which is constituted by using the phase-locked loop circuit is increased.
Therefore, a system which is suitable for the PRML signal processing should be realized by digitizing also a clock reproduction circuit and equalization means, thereby increasing the quality of reproduced data and reducing the cost by the integration also in the high-density recording and reproduction.
However, when the phase-locked loop circuit for performing the clock reproduction is realized by digital circuits, as a transfer rate is increased, a delay amount of the phase-locked loop is increased and a capture range indicating a range where a frequency and a phase can be locked at the phase locking is reduced. When phase error information is obtained from analog signals, an amount of a continuous time error can be handled. However, when the phase error information is obtained from digital data after the sampling, the phase error information should be assumed from an amplitude value in the vicinity of a zero cross point. Therefore, sufficient continuous areas of phase error signals cannot be secured.
When the capture range is reduced, in a case where the frequency of the reproduction clo

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