Phase-locked loop apparatus

Details Phase-locked loop apparatus Phase-locked loop apparatus

1990-02-16

1991-01-29

Pascal, Robert J.

Oscillators

Automatic frequency stabilization using a phase or frequency...

Plural a.f.s. for a single oscillator

331DIG2, H03L 708

Patent

active

049889559

ABSTRACT:
A clock signal having a predetermined frequency output from a clock generator and a signal output from a voltage controlled oscillator (VCO) and supplied through a frequency divider are supplied to a phase detector. An output from the phase detector is supplied to a loop filter. The loop filter supplies a voltage in accordance with an output from the phase detector to a first control voltage terminal of the VCO and to a phase lock-in circuit. The phase lock-in circuit supplies a voltage in accordance with an output voltage from the loop filter to a second control voltage terminal of the VCO. In the VCO, the sensitivity of the first control voltage terminal is lower than that of the second control voltage terminal, i.e., a rate of change in ouput frequency with respect to a change in second control voltage is higher than that of the first control voltage. A phase lock detector for detecting whether or not the PLL apparatus is set in a phase-locked state is also connected to the phase lock-in circuit. When the phase lock detector detects a phase-locked state, a trigger signal is supplied to a power Vi turn off circuit to turn off a power source Vi. The power source Vi is connected to the clock generator, the phase detector, a part of the phase lock-in circuit, the phase lock detector, and the frequency divider. Power is always supplied from a power source Vc to the remaining circuit of the phase lock-in circuit.

REFERENCES:
patent: 4297650 (1981-10-01), Shinmyo

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