Phase-locked loop and resulting frequency multiplier

Details Phase-locked loop and resulting frequency multiplier Phase-locked loop and resulting frequency multiplier

1994-10-03

1996-08-20

Wong, Peter S.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

327160, 327116, 327119, H03K 500

Patent

active

055482350

ABSTRACT:
The frequency multiplier 20 is embodied by a phase-locked loop including a phase comparator 11 for commanding a plurality of delay elements 130 to 137 that furnish successive phase-shifted signals CL0-CL7 to a logical adder 16 made up of EXCLUSIVE OR gates.

REFERENCES:
patent: 3587043 (1971-06-01), Mengani
patent: 3993957 (1976-11-01), Davenport
patent: 4715050 (1987-12-01), Tanaka et al.
patent: 4795985 (1989-01-01), Gailbreath, Jr.
patent: 4873491 (1989-10-01), Wilkins
patent: 4912433 (1990-03-01), Motegi et al.
patent: 4922141 (1990-05-01), Lofgren et al.
patent: 5043596 (1991-08-01), Masuda et al.
patent: 5079519 (1992-01-01), Ashby et al.
patent: 5087829 (1992-02-01), Ishibashi et al.
IBM Technical Disclosure Bulletin, vol. 26, No. 3A, Aug. 1983, pp. 990, 991, Hernandex, Jr., "Frequency Multiplier Using Delay Circuits".

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