Phase-locked loop and resulting frequency multiplier

Details Phase-locked loop and resulting frequency multiplier Phase-locked loop and resulting frequency multiplier

1998-11-16

2000-11-21

Lam, Tuan T.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Frequency or repetition rate conversion or control

327119, 377 47, H03K 500

Patent

active

061508551

ABSTRACT:
The frequency multiplier 20 is embodied by a phase-locked loop including a phase comparator 11 for commanding a plurality of delay elements 130 to 137 that furnish successive phase-shifted signals CL0-CL7 to a logical adder 16 made up of EXCLUSIVE OR gates.

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Japan Citation No. 63-298514; Relevance: Fig. 1, Figs 2a and 2b.
Japanese Patent Appln No. 56-60311 filed Apr. 21, 1981; Hideyuki Ohara "A skew adjusting circuit", Applicant: Fujitsu Limited.
Japanese Patent Appln. No. 60-74131 filed Apr. 8, 1985, Applicant Sumitomo Electric Industries, Ltd., Akira Fukuda, "A Phase Comparator".
IBM Technical Disclosure Bulletin, vol. 26, No. 3A, Aug. 1983, pp. 990,991, Hernandex, Jr., "Frequency Multiplier Using Delay Circuits".

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