Phase locked loop and method that provide fail-over...

Details Phase locked loop and method that provide fail-over... Phase locked loop and method that provide fail-over...

2001-11-26

2004-05-04

Le, Amanda T. (Department: 2634)

Pulse or digital communications

Synchronizers

Synchronization failure prevention

C375S376000, C327S147000, C327S156000

Reexamination Certificate

active

06731709

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to phase-locked loop (PLL) circuits, and, more particularly, to a PLL that is configured to fail-over from one input clock signal to another input clock signal without losing lock.
DESCRIPTION OF THE RELATED ART
The need to generate a local signal which is synchronized with an external reference signal is critical in many electronics applications such as frequency synthesis, clock recovery, clock generation and frequency demodulation. This coherence between the reference signal and the local replica is referred to as “phase synchronization”. This implies either that local signal is typically either in phase with the external reference signal or is offset from the reference signal by some phase constant.
At the heart of any such synchronization circuit is some form of a phase locked loop (PLL). Phase-locked loops are feedback control loops, whose controlled parameter is the phase of a locally generated replica of an incoming reference signal. Phase-locked loops have three basic components: a phase detector, a loop filter, and a voltage-controlled oscillator.
FIG.
1
—Basic PLL
A basic schematic diagram of a typical PLL
100
is presented in FIG.
1
. As shown, PLL
100
is configured to generate an output signal
120
in response to an input signal
112
. PLL
100
includes a phase detector
114
, a loop filter
116
, and a voltage-controlled oscillator (VCO)
118
. Phase detector
114
is coupled to receive input clock signal
112
and to produce output clock signal
120
. Phase detector
114
measures the phase difference between signals
112
and
120
, and generates a phase error signal
115
, which may be a voltage indicative of this phase difference. In some instances, phase detector
114
may also generate a signal even when there is no difference between signals
112
and
120
. As signals
112
and
120
change with respect to each other, signal
115
becomes a time-varying signal into loop filter
116
. This phase comparison is necessary to prevent output signal
120
from drifting with respect to reference signal
112
. As shown, the feedback signal
121
is an internal part of the PLL
100
. It is noted, as is shown below, that the feedback signal
121
may be a signal external to the PLL
100
.
Loop filter
116
governs the response of PLL
100
to the error detected between signals
112
and
120
. A well-designed loop filter
116
should be able to track changes in the incoming signal's phase but should not be overly responsive to signal noise. Loop filter
116
generates an error correction signal
117
, which is the input to VCO
118
. In one embodiment, a zero voltage on signal
117
causes the output of VCO
118
, output signal
120
, to oscillate at a predefined frequency, &ohgr;
0
, which is the “center” frequency of the oscillator. On the other hand, a positive voltage on error correction signal
117
causes output signal
120
to oscillate at a frequency which is greater than &ohgr;
0
. Conversely, a negative voltage on error correction signal
117
causes output signal
120
to oscillate at a frequency less than &ohgr;
0
. In another embodiment, described below, either a positive voltage or a negative voltage on error correction signal
117
is generated. In this embodiment, even when there is no difference between signals
112
and
120
, an error correction signal
117
is output. In still another embodiment, the error correction signal
117
is scaled such that although the error correction signal
117
is always of one sign, such as always positive, the error correction signal
117
corrects for oscillation either above or below the predefined frequency.
Generally speaking, in many embodiments, the output frequency of VCO
118
is a linear function of its input voltage over some range of input and output. “Phase lock” is achieved by feeding the output of VCO
118
back to phase detector
114
so that continual error correction may be performed. It is noted that PLL
100
may not achieve phase lock if reference signal
112
is outside of some predetermined range.
In its simplest form, loop filter
116
is simply a conductor; that is, phase error signal
115
is equal to error correction signal
117
. Such a filter
116
allows PLL
100
to generate an output signal
120
which matches reference signal
112
in frequency and phase only if reference signal
112
is equal to the center frequency of VCO
118
. If reference signal
112
oscillates at a different frequency from the center frequency of VCO
118
, output signal
120
may match reference signal
112
in frequency but not phase. This “wire filter” is an example of a first-order PLL, which means that the denominator of the loop filter transfer function has no exponent value greater than one. In another embodiment of a first-order PLL, loop filter
116
includes an amplifier.
FIG.
2
—PLL with Multiple Clock Inputs
Second-order PLLs, such as shown in
FIG. 2
, are more commonly used than first-order PLLs
100
. The second-order PLL
200
, as shown, also incorporates a mechanism for switching input clock signals between a first clock source
222
A and a second clock source
222
B. It is noted that the first clock source
222
A and the second clock source
222
B are preferably synchronized in frequency and in phase. The selection of the input clock signal from the first clock source
222
A or the second clock source
222
B may be made by a SEL_CLK input or by the switching logic
230
. Switching logic
230
receives CONTROL inputs and outputs STATUS information. The input clock signal is provided to a phase detector
214
. The phase detector outputs a phase error signal
215
as a combination of UP and/or DOWN pulses. These UP and DOWN pulses are typically digital signals indicative of the phase difference between the input clock signal and the feedback signal
221
. The UP pulse is indicative of a phase difference between the feedback signal
221
and the input clock signal when an edge of the feedback signal
221
occurs after a corresponding edge of the input clock signal. The DOWN pulse is indicative of a phase difference between the feedback signal
221
and the input clock signal when an edge of the feedback signal
221
occurs before a corresponding edge of the input clock signal.
One difference between the first-order PLL
100
and the second-order PLL
200
is that the second-order PLL has an integrating loop filter
216
. A second order loop filter
216
performs an integration function, such as that typically found in a low-pass filter. This functionality allows the second-order PLL
200
to generate an output signal
220
which matches reference signal
212
in phase and frequency when reference signal
222
is not identical to the center frequency of VCO
218
. This is possible since the second-order loop filter is configured to generate a non-zero error correction signal even when signals
222
and
220
match in phase. This non-zero error correction signal allows VCO
218
to oscillate at above or below its center frequency while remaining in phase with reference input clock signal
222
.
It is noted that third-order (and possibly higher-order) PLLs exist and are commonly used in circuits such as those used in cellular and satellite communications. Third-order PLLs include third-order loop filters configured to perform double integration, which allows frequency and phase synchronization to occur even with a Doppler shift between the reference clock signal and output signal. It is also noted that multipliers and/or dividers are also used to generate an output signal, which is different, such as in frequency or phase, than the reference input signal.
An important feature of the PLL
200
of
FIG. 2
is the ability to switch between an input clock signal
222
A from a first clock source and the input clock signal
222
B from a second clock source. The switching logic
230
is configured to detect a failure of the input clock signal
222
A from the first clock source and to cause the input clock signal
222
B from the second clock sourc

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