Phase-locked loop and method for operating a phase-locked-loop

Oscillators – Automatic frequency stabilization using a phase or frequency... – Afc with logic elements

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C331S016000, C331S034000, C331S17700V, C331S025000, C327S156000, C327S157000, C375S376000

Reexamination Certificate

active

11584318

ABSTRACT:
A phase-locked loop suitable for mobile radio communications and a method for operating the same is disclosed. One embodiment of the phase-locked loop comprises an oscillator, a counter, a comparator, and a delay arrangement. The counter comprises a first input connected to the oscillator, a second input connected to a reference frequency terminal, and an output. An input of the comparator is connected to the output of the counter and an output of the comparator to the oscillator. The delay arrangement is connected between the oscillator and the first input of the counter or between the reference frequency terminal and the second input of the counter. The delay arrangement delays an input signal sent to an input of the delay arrangement, as a function of a sequence signal and makes a delayed signal available at an output of the delay arrangement.

REFERENCES:
patent: 6094101 (2000-07-01), Sander et al.
patent: 6160456 (2000-12-01), Chang
patent: 6219394 (2001-04-01), Sander
patent: 6269135 (2001-07-01), Sander
patent: 6658748 (2003-12-01), Leipold et al.
patent: 6952138 (2005-10-01), Hagberg et al.
patent: 7279993 (2007-10-01), Bruno et al.
patent: 2002/0043992 (2002-04-01), McCune, Jr. et al.
patent: 2002/0168043 (2002-11-01), Sander
patent: 2003/0234693 (2003-12-01), Staszewski et al.
patent: 2004/0057547 (2004-03-01), Henrickson
patent: 2004/0247041 (2004-12-01), Biedka et al.
patent: 1 255 355 (2002-11-01), None
patent: WO 03/023951 (2003-03-01), None
“Delta-Sigma Modulators Using Frequency-Modulated Intermediate Values”, Mats Høvin, Alf Olsen, Tor Sverre Lande and Chris Toumazou, IEEE Journal of Solid-State Circuits, vol. 32, No. 1, Jan. 1997, pp. 13-22.
“A Novel Multi-Bit Parallel Delta-Sigma FM-to-Digital Converter with 24-Bit Resolution”, Dag T. Wisland, Mats E. Høvin and Tor S. Lande, ESSCIRC 2002, pp. 687-690.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Phase-locked loop and method for operating a phase-locked-loop does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Phase-locked loop and method for operating a phase-locked-loop, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Phase-locked loop and method for operating a phase-locked-loop will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3908699

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.