Phase-locked loop and delay-locked loop including...

Details Phase-locked loop and delay-locked loop including... Phase-locked loop and delay-locked loop including...

2007-02-13

2007-02-13

Tra, Quan (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

C327S158000, C327S266000, C327S274000, C327S287000, C331S057000

Reexamination Certificate

active

10876730

ABSTRACT:
A differential delay cell is provided herein that not only receives a pair of differential input values, but also receives a pair of differential control values for delaying the differential input values to produce a pair of differential output values. As such, a delay cell is provided, which is truly differential, and therefore, capable of demonstrating a significant improvement in noise performance. The differential delay cell of the present invention also demonstrates high frequency stability around the center frequency, constant gain and increased tuning range capabilities. In this manner, the differential delay cell may be used in PLL or DLL designs as part of a low noise VCO or a low noise delay line, respectively.

REFERENCES:
patent: 4939518 (1990-07-01), Hotta et al.
patent: 5172076 (1992-12-01), Brown
patent: 5396131 (1995-03-01), Miki et al.
patent: 5440515 (1995-08-01), Chang et al.
patent: 5489878 (1996-02-01), Gilbert
patent: 5789989 (1998-08-01), Paschal et al.
patent: 5867778 (1999-02-01), Khoury et al.
patent: 5994939 (1999-11-01), Johnson et al.
patent: 6900703 (2005-05-01), Garvin
patent: 2003/0201815 (2003-10-01), Tung et al.
International Search Report, PCT/US2004/021035, mailed Nov. 3, 2004.
Park et al., “A Low-Noise, 900-MHz VCO in 0.6-μm CMOS,” IEEE Journal of Solid-State Circuits, vol. 34, No. 5, May 1999, pp. 586-591.
Maneatis, “Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques,” IEEE Journal of Solid-State Circuits, vol. 31, No. 11, Nov. 1996, pp. 1723-1732.

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