Phase locked loop and a motor control servo

Electricity: motive power systems – Braking – Automatic and/or with time-delay means

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318327, 318341, 318608, 318600, H02P 516, G05B 500

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active

045647941

ABSTRACT:
The speed of a DC motor (10) is controlled by a servo which includes a digital phase lock loop. The motor drives a tachometer whose pulse (22) frequency is low relative to the frequency of a clock (21). The clock continuously drives a counter (200) whose ever increasing number content is gated to a data latch (26) upon the occurrence of each successive tachometer pulse, thus this data latch contains a first time-number of ever increasing magnitude. A second data latch (24) contains a second number. The difference in magnitude of two consecutive time-numbers is indicative of motor speed. Initially, this second number is set to contain a reference number (REF) which is equal in magnitude to the number of clock pulses which will occur between adjacent tachometer pulses when the motor is running at desired speed. A pair of limit numbers (RANGEL and RANGEH) are provided to define the upper and lower limits of servo saturation. The difference between the first number and the second number is detected upon the occurrence of each tachometer pulse to generate a third or difference number (ERRA). This difference number is compared to the two limit numbers to determine if the servo is in saturation. If it is not in saturation, the second number is reset to a value which is equal to the old value plus the reference number. If the servo is in saturation, the second number is reset to a number which is a function of the first number, the reference number, and that limit number which is associated with the particular mode of saturation.

REFERENCES:
patent: 3936762 (1976-02-01), Cox, Jr. et al.
patent: 4027215 (1977-05-01), Knight et al.
patent: 4243921 (1981-01-01), Tamura et al.
patent: 4254367 (1981-03-01), Sakamoto
patent: 4287461 (1981-09-01), Promis et al.
patent: 4492903 (1985-01-01), Knight et al.
patent: 4500822 (1985-02-01), Tajima et al.
patent: 4504960 (1985-03-01), Yamada
IBM Technical Disclosure Bulletin, vol. 23, No. 11, Apr. 1981, "Digital Phase Error Detector", by L. Taber, pp. 5171-5173.

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