Phase-locked loop

Details Phase-locked loop Phase-locked loop

1999-12-17

2001-04-24

Mis, David (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Particular error voltage control

C331S008000, C331S025000, C327S156000, C327S157000

Reexamination Certificate

active

06222421

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a phase-locked loop, and more particulary, to frequency stabilization of an oscillation output signal generated by a phase-locked loop. The present invention further relates to a current drive type charge pump circuit and a voltage-controlled oscillator of the phase-locked loop.
FIG. 1
is a schematic block diagram showing a conventional phase-locked loop (PLL)
100
.
FIG. 2
is a timing chart illustrating the operation of a phase comparator
1
of the PLL
100
.
The PLL
100
includes the phase comparator
1
, a charge pump circuit
2
, a low-pass filter (LPF)
3
, and a voltage-controlled oscillator (VCO)
4
. The phase comparator
1
compares the phase of a reference clock signal RK with the phase of an oscillation clock signal CK, which is generated by the VCO
4
, and generates comparison output signals PP, PN in accordance with the phase difference between the reference clock signal RK and the oscillation clock signal CK. For example, as shown in
FIG. 2
, when the phase of the reference clock signal RK is ahead of the phase of the oscillation clock signal CK, the comparison output signal PN goes high. On the other hand, when the phase of the reference clock signal RK is behind or delayed from that of the oscillation clock signal CK, the comparison output signal PP goes low.
The charge pump circuit
2
has transistors, which are activated and deactivated in response to the comparison output signals PP, PN, and sends a charge pump output signal PD, which corresponds to the comparison output signals PP, PN, to the LPF
3
. For example, the charge pump output signal PD is lowered to the ground voltage when the comparison output signal PN goes high and raised to the power supply voltage when the comparison output signal PP goes low. When the comparison output signal PP is high and the comparison output signal PN is low, all of the transistors are deactivated and the output terminal of the charge pump circuit
2
enters a high impedance state.
The LPF
3
removes the alternating current components from the charge pump output signal PD and provides a control voltage Vc to the VCO
4
. The control voltage Vc fluctuates in accordance with the pulse width of the output signal PD. Accordingly, the control voltage Vc decreases when the charge pump output signal PD becomes equal to the ground voltage and increases when the charge pump output signal PD becomes equal to the power supply voltage.
The VCO
4
is provided with, for example, a ring oscillator and alters the frequency of the oscillation clock signal CK by increasing or decreasing the delay amount of the feedback loop in response to the control voltage Vc.
In the LPF
3
, when the phase of the reference clock signal RK is offset from that of the oscillation clock signal CK, the oscillation frequency of the VCO
14
is controlled in a direction opposite the offset direction. In this manner, the oscillation clock signal CK is synchronized with the reference clock signal RK.
In the charge pump circuit
2
, it is desirable that the current flowing out through the output terminal in response to a low comparison output signal PP be substantially equal to the current flowing in through the output terminal in response to a high comparison output signal PN. When the current flowing in through the output terminal becomes unequal to the current flowing out through the output terminal, the phase difference between the reference clock signal RK and the oscillation clock signal CK becomes biased and hinders stable operation of the LPF
3
. As a result, external noise may destabilize the operation of the LPF
3
. Furthermore, the phase lock may be released.
A current drive type charge pump circuit is one type of a charge pump circuit used for an LPF. A current drive type charge pump circuit is provided with a CMOS transistor, which has a current capacitance that is sufficient for driving a load capacitor connected to the output terminal and which charges and discharges the load capacitor in response to an input signal. In this type of charge pump circuit, it is desirable that the current flowing out to the load during charging be substantially equal to the current flowing in from the load during discharging. Accordingly, it is preferable that a CMOS transistor having substantially identical p-channel and n-channel transistor operational characteristics be used.
FIG. 3
is a schematic circuit diagram illustrating a current drive type charge pump circuit
200
, and
FIG. 4
is a graph illustrating the operational characteristics of a CMOS transistor employed in the charge pump circuit
200
.
A p-channel MOS transistor
201
and an n-channel MOS transistor
202
are connected in series between a high potential power supply and a ground. A first comparison output signal PP is applied to the gate of the transistor
201
, while a second comparison output signal PN is applied to the gate of the transistor
202
. A charge pump output signal PD is output from a node located between the transistors
201
,
202
. When the transistor
201
is activated in response to the first comparison output signal PP, a charging current Ip flows through the transistor
201
to charge the load capacitor (not shown) connected to the output terminal. When the transistor
202
is activated in response to the second comparison output signal PN, a discharging current In flows through the transistor
202
to discharge the load capacitor connected to the output terminal. A p-channel MOS transistor
203
, functioning as a current control load, is connected between the transistor
201
and the high potential power supply. An n-channel MOS transistor
204
is connected between the transistor
202
and the ground. A first control voltage Vcp provided by a bias circuit
209
is applied to the gate of the transistor
203
, and a second control voltage Vcn provided by the bias circuit
209
is applied to the gate of the transistor
204
.
The bias circuit
209
includes a resistor
205
and transistors
206
-
208
. The resistor
205
and the n-channel MOS transistor
206
are connected in series between the high potential power supply and the ground. A node A located between the resistor
205
and the transistor
206
is connected to the gate of the transistor
206
. The p-channel MOS transistor
207
and the n-channel MOS transistor
208
are connected in series between the high potential power supply and the ground. A node B located between the transistors
207
,
208
is connected to the gate of the transistor
207
. The gate of the transistor
208
is connected to the node A. The transistors
207
,
208
form a current mirror circuit relative to the resistor
205
and the transistor
206
. The second control voltage Vcn applied to the n-channel transistor
204
is provided from the node A, and the first control voltage Vcp applied to the p-channel transistor
203
is provided from the node B. The current mirror operation of the bias circuit
209
optimally maintains the currents Ip, In flowing through the corresponding transistors
201
,
202
at a constant value.
Even if the voltage applied to the gates of the transistors
201
,
202
are constant, the currents Ip, In fluctuate in accordance with the voltage at the output terminal. Current does not flow unless there is a voltage difference between the source and the drain even if voltage is applied to the gate. Thus, the currents Ip, In do not flow when the transistor
201
is activated with the load capacitor in a charged state or when the transistor
202
is deactivated with the load capacitor in a discharged state. The fluctuation of the currents Ip, In relative to the voltage at the output terminal is shown in FIG.
4
. That is, the current Ip flowing through the transistor
201
starts to increase when the voltage at the output terminal becomes lower than the power supply voltage Vdd and keeps increasing until reaching a predetermined value I
0
. After the current Ip reaches the predetermined value I
0
, the increase of the current Ip, relative to the decre

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