Phase locked loop

Details Phase locked loop Phase locked loop

2008-01-01

2008-01-01

Pascal, Robert (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Plural a.f.s. for a single oscillator

C331S016000, C331S017000, C331S025000, C331S014000, C327S157000

Reexamination Certificate

active

11400062

ABSTRACT:
A phase locked loop includes a controlled oscillator for delivering an output signal at a determined output frequency, and a variable frequency divider for converting the output signal into a signal at divided frequency. The PLL is termed composite in that it includes at least one first loop having a loop filter for generating a first control signal for the oscillator on the basis of the signal at divided frequency, and a second loop having a loop filter, different from the loop filter of the first loop, for generating, on the basis of the signal at divided frequency, a second signal for additional control of the oscillator. The loop filter of the first loop and the loop filter of the second loop have different respective cutoff frequencies. The passband of the first loop, can be adapted to ensure the convergence and the stability of the PLL, while the second loop can afford extra passband increasing the speed of adaptation of the PLL in case of modification of the value of a preset for the output frequency.

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FR Search Report for FR 0503480; Oct. 27, 2005.
Herzel, et al. “An Integrated CMOS RF Synthesizer for 802.11a Wireless Lan”; IEEE Journal of Solid State Circuits; Oct. 2003; pp. 1767-1770; vol 38, No. 10.

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