Phase locked loop

Details Phase locked loop Phase locked loop

1998-07-20

2002-08-27

Corrielus, Jean (Department: 2631)

Pulse or digital communications

Spread spectrum

C331S023000, C375S376000, C327S156000

Reexamination Certificate

active

06442188

ABSTRACT:

BACKGROUND
The invention relates to a phase locked loop.
A typical computer system uses clock signals to synchronize operations of digital circuitry of the system. Unfortunately, spectral components of these clock signals may radiate electromagnetic interference (EMI) emissions. For example, referring to
FIG. 1
, the spectral components of a clock signal might include a spectral component
10
that is located at a fundamental frequency (called f
O
and may be, for example, 100 MHz) of the signal as well as spectral components
12
that are located at harmonic frequencies (i.e., frequencies located at multiples of the f
O
frequency).
The EMI emissions may cause undesirable interference with the circuitry of the computer system and other electronic equipment near the computer system. To reduce the EMI emissions, the circuitry of the computer system may be housed inside a metal casing which prevents the EMI emissions from propagating outside of the casing. However, the casing often adds to the weight and cost of the computer system, and the casing has a limited shielding capability.
In addition to the casing, the EMI emissions may be further reduced by spread spectrum clocking (SSC) which reduces the energy peaks present in the spectral components of the clock signal. In SSC, a spread spectrum clock signal (called CLK
IN
(see FIG.
2
)) may be generated by an SSC generator
14
. To accomplish this, the SSC generator
14
might receive a signal (from a reference generator
13
) which indicates a nominal fundamental frequency (called f
NOM
) for the CLK
IN
signal. The SSC generator
14
uses the f
noM
frequency to generate the CLK
IN
signal which has, in place of a constant fundamental frequency, a time-varying frequency (called f
SSC
(see FIG.
3
)) that deviates slightly (within 1 MHz, for example) about the f
NOM
frequency. As a result of the modulation of the fundamental frequency, spectral components
18
(see
FIG. 1
) of the CLK
IN
clock signal have typically smaller magnitudes than the corresponding spectral components
10
and
12
of the traditional clock signal, and as a result, the CLK
IN
signal typically generates fewer EMI emissions.
Referring to
FIG. 3
, over one cycle, the f
SSC
frequency may deviate about the F
NOM
frequency between a minimum frequency (called f
L
) and a maximum frequency (called f
H
). The f
SSC
frequency may, for example, resemble a sawtooth waveform
5
or may resemble a linear and cubic combination
7
of the sawtooth waveform
5
. The frequency at which the f
SSC
frequency cycles is often called an SSC modulation frequency (called f
M
) of the CLK
IN
signal and may be higher than audio frequencies (20 Hz to 20 kHz frequencies) but significantly lower than the F
NOM
frequency. As examples, the f
M
frequency might be near 33 kHz, and the F
NOM
frequency might be near 100 MHz.
Referring back to
FIG. 2
, phase locked loops (PLLs) are often used to regenerate clock signals to minimize the effects of parasitic impedances of transmission lines that are used to communicate the clock signals. In this manner, a PLL
15
may receive and lock onto the CLK
IN
signal to generate another spread spectrum clock signal (called CLK
OUT
) that might ideally be a duplicate of the CLK
IN
signal.
However, referring to
FIGS. 4 and 5
, the CLK
OUT
signal is typically not an exact duplicate of the CLK
IN
signal but instead, may lead or lag the CLK
OUT
signal in time by a phase error, or clock skew (called T
S
). For purposes of the following description, the clock skew T
S
is defined as an interval of time in which the CLK
IN
signal undesirably leads the CLK
OUT
signal and might assume a negative (when the CLK
IN
signal lags the CLK
OUT
signal) or a positive (when the CLK
IN
signal leads the CLK
OUT
signal) value.
As an example, one SSC modulation cycle, the f
SSC
frequency (see
FIG. 3
) periodically decreases (during time T
1
to time T
2
, for example) from the f
H
to the f
L
frequency to produce a resultant skew T
S
20
(see
FIG. 6
) that approaches a large negative value (a value near −1000 picoseconds (ps), for example). Thus, during this time interval, the CLK
IN
signal may lag the CLK
OUT
signal due to the decrease in frequency. Once the f
SSC
frequency reaches the f
L
frequency (at time T
2
, for example) and then abruptly changes course and rises upwardly (after time T
2
, for example) toward the f
H
frequency, the skew T
S
20
may approach a large positive value (1000 ps) due to the increase in frequency and the PLL's temporary over compensation.
One way to decrease the skew is to increase the response speed of the PLL
15
, and one way to increase the response speed of the PLL
15
is to increase the PLL's bandwidth. For example, the large skew T
S
20
may occur when the PLL
15
has a relatively low bandwidth (a bandwidth of 440 kHz, for example), but when the PLL
15
has a larger bandwidth (a bandwidth of 1.2 MHz, for example), a resultant skew T
S
21
(see
FIG. 6
) may be much smaller (the skew T
S
may deviate between 140 and −140 ps, as an example). However, even with this reduction, the skew T
S
21
may not be sufficient to satisfy timing requirements of the computer system.
Thus, there is a continuing need for an arrangement to reduce the skew of such a system.
SUMMARY
In one embodiment, a method includes locking onto a phase of a spread spectrum clock signal to minimize a phase error between an output clock signal and the spread spectrum clock signal. The spread spectrum clock signal has a time-varying frequency that cycles at a modulation frequency, and the spread spectrum and output clock signals are approximately separated by the phase error. The method includes minimizing a phase angle between spectral components of the output and spread spectrum clock signals near the modulation frequency.
In another embodiment, a phase locked loop minimizes a phase error between a spread spectrum clock signal and an output clock signal. The phase locked loop includes a detector and a filter. The detector receives a spread spectrum clock signal and compares the spread spectrum clock signal with an output signal. The spread spectrum clock signal has a time-varying frequency that cycles at a modulation frequency. The filter is coupled to the detector to minimize a phase angle between spectral components of the output and spread spectrum clock signals near the modulation frequency.


REFERENCES:
patent: 5414741 (1995-05-01), Johnson
patent: 5488627 (1996-01-01), Hardin et al.
patent: 5506545 (1996-04-01), Andrea
patent: 5631920 (1997-05-01), Hardin
patent: 5822011 (1998-10-01), Rumreich
patent: 5867524 (1999-02-01), Booth et al.
patent: 5872807 (1999-02-01), Booth et al.
patent: 5909144 (1999-06-01), Pukette et al.
patent: 6046646 (2000-04-01), Lo et al.
patent: 6046735 (2000-04-01), Bassetti et al.
Keith B. Hardin, et al., “Design Considerations of Phase-Locked Loop Systems for Spread Spectrum Clock Generation Compatibility” pp. 1-6, presented at the 1997 IEEE International Symposium on Electromagnetic Compatibility, Austin, TX, Aug. 18-22.
Andrew Volk, et al., “Notes on AGP Interface Architectures and Motherboard Design with SSC”, pp. 1-7, Feb. 1998.

Affiliated with

Also associated with

Rating

Phase locked loop does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Phase locked loop, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Phase locked loop will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2895782