Phase locked loop

Details Phase locked loop Phase locked loop

2001-01-10

2002-03-12

Cunningham, Terry D. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C375S375000

Reexamination Certificate

active

06356127

ABSTRACT:

FIELD
The present invention relates generally to phase locked loops (PLLs).
BACKGROUND
Access equipment for telecommunications networks continues to evolve, with faster communications both desired and needed. Standards for such communications are also changing to accommodate increased available and necessary bandwidths, increased amounts of traffic, and the like. In order to keep pace with the ever-increasing speed and detail requirements of telecommunications systems, telecommunications equipment must also continue to advance. To that end, components are becoming smaller, communications are becoming faster, and error tolerances in such systems are dropping.
A typical access system for a telecommunications network is a digital loop carrier (DLC) platform, for example, the DCS-40, available from ADC Teledata, Herzliya, Israel. A typical DLC product consists of one or more remote terminals or units connected, often in a ring configuration, to a central unit or central office unit. The central office unit or terminal is connected to a switch by analog or digital interfaces. Transmission occurs between the central office terminal and the subscriber interfaces or remote units. Development of integrated synchronous digital hierarchy (SDH) and synchronous optical network (SONET) interfaces for this platform include a connection between the remote unit or units and the central unit over a high speed optical ring. SDH or SONET cards are integrated into the central and remote units.
Phase locked loops (PLLs) are used in communications equipment such as central and remote units of a DLC for locking the clocks of multiple units together so that all components of the system run at the same clock rate. A PLL is a mechanism by which timing information is transferred within a data stream and the receiver derives the signal element timing by locking its local clock to a reference clock. As communications equipment has continued to increase in complexity, speed, capability, the need for better and more accurate PLLs has become greater.
SUMMARY
In one embodiment, a method of locking a local clock to a reference clock includes dividing the local clock into a number of phases, and counting the total number of rising and falling edges of the local clock in a bank of difference counters. The total number of rising and falling edges in a predetermined time period is periodically summed by a summation counter, and the sum is compared to a stored summed total number of rising and falling edges in an identical earlier time period. The local clock is adjusted if the compared summed and stored totals differ by more than a predetermined amount.
In another embodiment, a phase locked loop includes a phase detector having a local clock signal input and a counter signal output. The phase detector includes a divider connected to the local clock signal input, a number of difference counters connected to receive divided signals from the divider, and a summation counter connected to the outputs of each of the difference counters and connected to receive an external latch signal to trigger summation of the difference counters.
Other embodiments are described and claimed.


REFERENCES:
patent: 5705945 (1998-01-01), Wee
patent: 6064707 (2000-05-01), Woodman, Jr.
patent: 6073259 (2000-06-01), Saetschev et al.
patent: 6107843 (2000-08-01), de Gouy et al.
patent: 6167103 (2000-12-01), Hardin
patent: 6292507 (2001-09-01), Hardin et al.

Affiliated with

Also associated with

Rating

Phase locked loop does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Phase locked loop, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Phase locked loop will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2881297