Phase-locked delay loop for clock correction

Details Phase-locked delay loop for clock correction Phase-locked delay loop for clock correction

1996-06-14

1998-09-29

Cunningham, Terry

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

327244, 327 5, 327276, H03L 700, H03K 500

Patent

active

058150161

ABSTRACT:
A controlled delay path inserts a selected delay into a clock distribution circuit to create a total clock delay that is equal to an integer number of clock cycles relative to a reference dock signal or which produces a selected phase relationship to the reference dock signal. The delay path correction of the invention is particularly useful in circuits having a wide range of possible system clock frequencies or having programmable routing of clock signals, and therefore a wide range of operating delays. A reference clock signal is directed to a range of selectable voltage controlled delay elements by a phase detector that receives the reference clock signal and a feedback signal, and that produces an error voltage which adjusts the voltage controlled delay elements to produce an output clock signal. Additional selectable delays may be included that create offset options and allow selection of a leading, lagging, or in-phase reference dock/output clock relationship. In one embodiment both the positive and negative edges of a clock signal are corrected. As another feature, if correction is consistently in the same direction an error flag is generated.

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