Phase-locked clock regeneration circuit for digital transmission

Details Phase-locked clock regeneration circuit for digital transmission Phase-locked clock regeneration circuit for digital transmission

1986-07-07

1989-04-18

Buczinski, Stephen C.

Pulse or digital communications

Spread spectrum

Direct sequence

370100, 375 20, H03D 324, H04L 2549, H04J 306

Patent

active

048233633

ABSTRACT:
In a digital transmission system, a clock regeneration circuit includes a phase-locked loop having a low-pass filter, a voltage-controlled oscillator connected thereto, and a phase comparator for supplying to the low-pass filter a signal representative of the phase difference between an incoming two-level data bit stream and the output of the voltage-controlled oscillator. The incoming data bit stream is converted into a plurality of parallel data bit streams and fed to a multi-level quadrature amplitude modulator in response to a clock signal derived from the output of the voltage-controlled oscillator and converted into an outgoing multi-level digital signal. An incoming CMI (coded mark inversion) coded binary signal is sampled by a flip-flop for in response to the output of the voltage-controlled oscillator to supply an output signal to the VCO through the low-pass filter.

REFERENCES:
patent: 3760111 (1973-09-01), Sawai
patent: 3983501 (1976-09-01), Lindstrum
patent: 4143322 (1979-03-01), Shimamura
patent: 4217551 (1980-08-01), Entenman
patent: 4393516 (1983-07-01), Itani
patent: 4571549 (1986-02-01), Lods et al.
patent: 4615041 (1986-09-01), Koskinen
patent: 4617679 (1986-10-01), Brooks
patent: 4635280 (1987-01-01), Smith et al.

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