Active solid-state devices (e.g. – transistors – solid-state diode – Thin active physical layer which is – Tunneling through region of reduced conductivity
Reexamination Certificate
1998-07-30
2001-02-27
Meier, Stephen D. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Thin active physical layer which is
Tunneling through region of reduced conductivity
C257S031000
Reexamination Certificate
active
06194737
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to novel structures of an arithmetic operation unit and a memory device, which utilize two phase states that are acquired by applying a DC bias voltage to single-electron tunneling (SET) junction elements via a series resistor and then applying an AC pump signal thereto to thereby allow the voltage between the junctions of the SET junction elements to be phase-locked to the AC pump signal, and a method of manufacturing the same.
2. Description of the Related Art
Recently have extensive studies been made on a single-electron tunneling effect which permits electrons to tunnel through a thin insulator layer with a small area, placed between two semiconductor layers or metal films, one by one. This invention provides novel structures of an arithmetic operation unit and a memory device, which utilize two stable phase states acquired by implementing phase-locking to an AC pump using the nonlinear characteristics that appear on a single-electron tunneling junction element (hereinafter simply called “SET junction element”) that produces such a single-electron tunneling effect.
A phase-locked arithmetic operation circuit and memory circuit which utilize such an SET junction element are disclosed in, for example, the paper written by the present inventor and entitled “Structure of Single-electron Tunneling Phase Logic” in Papers ED96-218 (March 1997) in Institute of Electronic Information Communication Engineering. A device which uses two phase states produced by applying a pump signal of twice the frequency of SET oscillation to an SET junction element has been proposed by Mr. Kiehl in Japanese Patent Application, KOKAI Publication No. 6-48213.
However, most of the conventional reports on SET junction elements simply cover their simulation analysis and operations, and no specific device architectures or no specific fabrication methods therefor have been proposed yet. While theoretically effective operations of phase-locked circuits using SET junction elements have been confirmed and are expected to solve problems of CMOS circuits, currently used widely, on dissipation power and the limited integration scale, which will surely arise in the near future, therefore, there is a strong demand of studying actual structures.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a novel structure of a phase-locked logic and memory circuit device, which use SET junction elements proposed by the present inventor et al., and a method of fabricating those devices.
To achieve this object, this invention is characterized in that a load resistor is constituted of a tunneling junction element, and a single-electron tunneling junction element and the tunneling junction element for load resistor are laminated to design a phase-locked circuit compact. Further, the load resistor is comprised of a plurality of laminated tunneling junctions for load resistor so that the load resistor can have the proper resistance. A DC bias voltage is applied to the electrode of the tunneling junction element for load resistor, and an AC pump voltage to one electrode of the single-electron tunneling junction element. In the case of a plurality of phase-locked circuit gates, one electrodes of the single-electron tunneling junction elements are designed into a common electrode to which the AC pump voltage is applied, and the other electrodes are formed apart from one another two-dimensionally. Then, the phase-locked circuit gates can be formed compact by laminating the tunneling junction elements for load resistor on the other electrodes.
To achieve the above structure, the dielectric constant of the insulator layer of the tunneling junction element for load resistor is made larger than that of the insulator layer of the single-electron tunneling junction element. Further, both insulator layers are formed to have substantially the same thickness. Furthermore, coupling capacitors between the gates are formed between the other electrodes of the single-electron tunneling junction elements, which are formed apart from one another.
To achieve the object, a phase-locked circuit device comprises:
a single-electron tunneling junction element having ultrasmall tunnel junction;
a tunneling junction element for resistance having one end connected to a first electrode of said single-electron tunneling junction element and an other end applied with a DC bias voltage, said tunneling junction element for resistance forming a load resistor; and
an AC voltage source for applying a voltage to a second electrode of said single-electron tunneling junction element,
a junction of said single-electron tunneling junction element being formed by a first insulator layer, a junction of said tunneling junction element for resistance being formed by a second insulator layer having a larger dielectric constant than that of said first insulator layer.
To achieve the object, according to this invention, a method of fabricating a phase-locked circuit device having a single-electron tunneling junction element and a load resistor, connected to said single-electron tunneling junction element and applied with a DC bias voltage, an AC pump voltage being applied to said single-electron tunneling junction element, said method comprises the steps of:
forming a first electrode of said single-electron tunneling junction element on a substrate;
forming a first insulator layer for forming a junction of said single-electron tunneling junction element on said first electrode;
forming a second electrode of said single-electron tunneling junction element on said first insulator layer;
forming a second insulator layer having a greater dielectric constant than that of said first insulator layer on said second electrode; and
forming on said second insulator layer an electrode for resistance constituting a tunnel junction for resistance constituting said load resistor and facing said second electrode,
wherein said tunnel junction for resistance is formed by said second electrode, said second insulator layer and said electrode for resistance.
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Armstrong, Westerman Hattori, McLeland & Naughton
Fujitsu Limited
Meier Stephen D.
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