Phase-lock loop with reduced acquistion time

Details Phase-lock loop with reduced acquistion time Phase-lock loop with reduced acquistion time

1996-02-16

1997-10-07

Pascal, Robert

Oscillators

Automatic frequency stabilization using a phase or frequency...

Particular error voltage control

331 25, 331 14, H03L 7093

Patent

active

056752911

ABSTRACT:
A control signal generation circuit is particularly suited for use in a phase lock loop circuit. The control signal generation circuit provides a control signal to a voltage controlled oscillator. The control signal is provided in response to a phase difference signal provided by phase comparator circuitry. Charge pump circuitry includes a primary current source that provides a primary current signal in response to the phase/frequency difference signal. A secondary current source provides a secondary current signal, also in response to the phase/frequency difference signal. The control signal generation circuit also includes filter circuitry. The filter circuitry includes a resistance element connected between a first input, which is connected to receive the primary current signal, and a second input, which is connected to receive the secondary current signal. A capacitance element, connected in series to the resistive element, is connected between the second input and ground. A voltage, relative to ground, is developed at the first input and is provided as the control signal.

REFERENCES:
patent: 5170130 (1992-12-01), Ichihara
patent: 5247265 (1993-09-01), Norimatsu
patent: 5276408 (1994-01-01), Norimatsu
patent: 5334953 (1994-08-01), Mijuskovic
patent: 5424689 (1995-06-01), Gillig et al.
patent: 5461344 (1995-10-01), Andoh
"Dual PLL IC Achieves Fastest Lock Time with Minimal Reference Spurs", RF Synthesizers National Semiconductor, William O. Keese, Aug. 1995, pp. 30-38.
"The Art Of Electronics" Second Edition, Paul Horowitz, Winfield Hill, Cambridge University Press, 1980, pp. 641-653.

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