Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
1998-08-07
2002-01-08
Lam, Tuan T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S159000, C331S011000
Reexamination Certificate
active
06337589
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a phase-lock loop (PLL), and more particularly, to a PLL with independent phase and frequency adjustment circuits that may be used in synchronous memory devices.
BACKGROUND ART
An external signal supplied to an electrical system is inevitably corrupted by additive noise. For various applications, such as clock generation, a highly stable signal is required. Therefore, the external signal should be processed to remove as much noise as possible.
To produce a stable internal signal based on the external signal, a conventional PLL may employ a current-controlled oscillator (CCO), whose frequency is controlled by a control current. A phase detector compares the phase of the external signal against the phase of the CCO output to determine an error signal that indicates the phase difference. To suppress noise, the error signal is averaged over some length of time, and the average value is used to produce the control current applied to the CCO to change its frequency in a direction that reduces the phase difference between the input signal and the CCO output.
Referring to
FIG. 1
, a conventional PLL
30
for producing a highly accurate internal clock INT.CLK based on an external reference clock EXT.CLK may comprise a phase detector
32
supplied with the EXT.CLK signal. Via a charge pump
34
, a loop filter
36
, and a voltage-to-current transformer
38
, the output of the phase detector
32
is coupled to a control input of a CCO
40
. A level shifting and buffering circuit
42
coupled to the CCO output produces the INT.CLK signal supplied via a feedback loop to the phase detector
32
.
The phase detector
32
compares the phase &PHgr;int of the INT.CLK signal with the phase &PHgr;ext of the EXT.CLK signal to generate a phase error voltage Vd=Kc(&PHgr;ext−&PHgr;int), where Kc is called the phase detector gain factor and is measured in units of volts per radian. The gain factor Kc is determined by the charge pump
34
used to charge and discharge the loop filter
36
.
The phase error voltage Vd is filtered by the loop filter
36
that suppresses noise and high-frequency components of the phase error signal. The voltage-to-current transformer
38
converts the filtered phase error voltage into control current that defines the frequency of the CCO
40
. The level shifting and buffering circuit
42
translates the level of the CCO output into a level required for a system supplied with the INT.CLK signal, and provides an interface between the PLL and this system.
When the loop is locked, the control current is such that the frequency of the CCO is equal to the average frequency of the EXT.CLK signal. For each cycle of the EXT.CLK signal there is one, and only one, cycle of the CCO output. To maintain the control current needed for lock, it is generally necessary to have a nonzero output from the phase detector. Consequently, the loop operates with some phase error present.
Since frequency is the derivative of phase, a conventional PLL performs frequency adjustment of an incoming signal simultaneously with adjustment of its phase. The frequency and phase adjustments are carried out using the phase detector
32
which performs phase comparison at the frequency of the CCO output signal supplied via the feedback loop. The error signal at the output of the phase detector
32
indicates instantaneous phase difference. The loop filter
36
provides averaging of the error signal over some time interval to establish an average value used for producing the control current applied to the CCO
40
. Deviation of the CCO from its center frequency caused by the control current may be described as d&PHgr;
0
/dt, where &PHgr;
0
is the phase of the CCO output equal to the phase &PHgr;int of the INT.CLK signal produced by the PLL
30
. In other words, a conventional PLL performs frequency and phase adjustments in the same loop.
A PLL starts out in an unlocked condition and must be brought into lock. The process of bringing a conventional PLL into lock is often a slow and unreliable process performed by the phase detector
32
that tracks variations of the INT.CLK signal with respect to the reference EXT.CLK signal. In particular, when the INT.CLK signal leads in phase with respect to the EXT.CLK signal, or the frequency of the INT.CLK signal is higher than the frequency of the EXT.CLK signal, the phase detector
32
causes the charge pump
34
to increase the potential at the output of the loop filter
36
. In response, the voltage-to-current transformer
38
reduces the value of the control current applied to the CCO
40
. As a result, the frequency of the INT.CLK signal at the output of the CCO
40
reduces. The reduction of the INT.CLK frequency causes the delay of the INT.CLK signal to reduce its phase lead with respect to the EXT.CLK signal.
By contrast, when the INT.CLK signal lags in phase with respect to the EXT.CLK signal, or the frequency of the INT.CLK signal is lower than the frequency of the EXT.CLK signal, the phase detector
32
causes the charge pump
34
to reduce the potential at the output of the loop filter
36
. In response, the voltage-to-current transformer
38
increases the value of the control current applied to the CCO
40
. When the control current increases, the frequency of the INT.CLK signal at the output of the CCO
40
increases. The INT.CLK frequency increase causes the INT.CLK signal to reduce its phase lag with respect to the EXT.CLK signal.
However, in conventional PLLs, it takes a long time to reach a locked state when the frequency of the INT.CLK signal becomes close to the frequency of the EXT.CLK signal. It would be desirable to provide a PLL that reduces the time required to bring the loop into a locked state.
If the INT.CLK frequency is close enough to the EXT.CLK frequency, a conventional PLL locks up with just a phase transient. There is no cycle slipping prior to lock. It would be desirable to provide a PLL that operates in a wide frequency range over which the loop could be brought into a locked state without slipping cycles.
A small phase error enables a PLL to maintain a locked state. However, if the error becomes so large that the CCO skips cycles, the PLL is considered to have lost lock. A recovery time is required to acquire lock again. It would be desirable to provide a PLL that requires a short recovery time.
DISCLOSURE OF THE INVENTION
Accordingly, one advantage of the present invention is in providing a PLL that reduces the time required to bring its loop into a locked state, compared to a conventional PLL.
Another advantage of the present invention is in providing a PLL that operates in a wide frequency range over which its loop can be brought into a locked state without slipping cycles.
A further advantage of the present invention is in providing a PLL that requires a short recovery time.
The above and other advantages of the invention are achieved, at least, in part, by providing a system for generating an internal clock signal in response to an external clock signal. The system comprises a phase adjustment circuit responsive to the external clock signal and the internal clock signal for producing a phase adjustment signal that represents difference between the phase of the external clock signal and the phase of the internal clock signal. A frequency adjustment circuit is responsive to the external clock signal and the internal clock signal for producing a frequency adjustment signal that represents difference between the frequency of the external clock signal and the frequency of the internal clock signal. A control value calculator is responsive to the phase adjustment signal and the frequency adjustment signal for producing a resulting control signal supplied to a signal-controlled oscillator that generates the internal clock signal at an internal clock frequency deviating in response to the resulting control signal.
In accordance with a first embodiment of the present invention, the frequency adjustment circuit may comprise a frequency detector responsive to the external and inte
Lam Tuan T.
McDermott & Will & Emery
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