Oscillators – Automatic frequency stabilization using a phase or frequency... – Particular error voltage control
Patent
1992-04-14
1993-11-02
Grimm, Siegfried H.
Oscillators
Automatic frequency stabilization using a phase or frequency...
Particular error voltage control
331 25, H03L 7093, H04L 702
Patent
active
052587258
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
The present invention relates to a phase lock loop circuit, and more particularly, to a phase lock loop circuit which suppresses jitter of a clock to be obtained from the phase lock loop circuit, and phase-locks that clock, so that the clock can follow up an externally input clock at high accuracy.
BACKGROUND ART
Phase lock loop circuits have been used in various electronic circuits. Here, a description will be given on a phase lock loop circuit which is used in the destuffing section of a PCM multiplexing/separating apparatus.
There is a stuffing synchronization system as a method for multiplexing data of multiple channels which are asynchronous. In this system, an extra pulse is inserted (stuffed) as needed into asynchronous data to increase the data speed before a multiplex operation and the channels are given a pseudo synchronous relation, and then the data is multiplexed to be transferred. A data-receiving side divides the multiplexed data channel by channel, and eliminates (destuffs) the extra pulse that a data-sending side has inserted to reproduce the original data. Since the reproduced data has data absent empty space from which the extra pulse has been removed, time dependent fluctuation (jitter) will occur in the flow of data. A jitter suppressor having a phase lock loop circuit is therefore provided in the destuffing section of the multiplexing/separating apparatus.
FIG. 1 exemplifies a destuffing section in a conventional multiplexing/separating apparatus.
Reference numeral "10" denotes a frequency divider which frequency-divides a received clock CKL. The frequency divider 10 starts frequency division when receiving an enable pulse ENA. The frequency-divided output is used as write address data for a memory 20 to store input data Din. The output of the most significant bit of the frequency divider 10 is sent to one of the input portions of a phase comparator 30.
The phase comparator 30 has the other input portion supplied with the output of the least significant bit of the frequency-divided output of a frequency divider 40, like the frequency divider 10. The frequency divider 40 frequency-divides the output from a voltage controlled oscillator (VCO) 70. The output of the frequency divider 40 is used as read address data for the memory 20.
Phase difference data from the phase comparator 30 is supplied to a low-pass filter (LPF) 50 to be smoothed, and after being amplified by an amplifier 60, it is then sent to the control terminal of the voltage controlled oscillator 70 to control an oscillation frequency.
The enable pulse ENA is sent from a timing generator (not shown) in the multiplexing/separating apparatus, in correspondence to valid data which is the received data excluding a frame sync pulse, a stuffing pulse, etc. The memory 20 is a dual port memory which can designate the write and read addresses, independently. The memory 20, like the frequency divider 10, is controlled in accordance with the enable pulse ENA, and only valid data in the received data is to be intermittently written in the memory 20.
In this destuffing section, the oscillation frequency from the voltage controlled oscillator 70 is so controlled as to provide the steady average of the phase differences between the write and read addresses of the memory 20. The data intermittently written in the memory 20 is read out through buffering as sequential data Dout which has an equal average speed, thereby suppressing the jitter.
The phase locked loop of the above-described destuffing section includes the phase comparator 30 of a digital type since phase comparison inputs are digital signals. The phase comparator 30 of a digital type can be easily realized by an exclusive-OR circuit, a set/reset flip-flop circuit, etc. Since the phase comparison output includes analog information for controlling the frequency from the voltage controlled oscillator 70, however, it is necessary to stabilize the amplitude of a fanout with resect to changes in temperature and voltage. In other words, a change in the amplitude of
REFERENCES:
patent: 5057705 (1991-10-01), Uchikoshi
Grimm Siegfried H.
Kabushiki Kaisha Toshiba
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