Phase lock loop with a multiphase oscillator

Details Phase lock loop with a multiphase oscillator Phase lock loop with a multiphase oscillator

2011-03-15

2011-03-15

Chang, Joseph (Department: 2817)

Oscillators

Polyphase output

C331S016000

Reexamination Certificate

active

07907023

ABSTRACT:
A phase lock loop utilizes a multiphase oscillator having a plurality of digital inputs. A plurality of DQ flip-flops, offset in time from each other generate a plurality of control signals to remove control phase information from the oscillator in digital form. A DQ flip-flop connected between any two digital inputs on the oscillator determines direction of the traveling wave. The direction and phase information address a look-up table to determine the current fractional phase of the oscillator. A divide by N circuit is used to reduce the oscillator frequency. A total phase indicator signal for the oscillator is determined using the current fractional phase. The total phase is compared to a reference phase to produce a control signal for making adjustments to the oscillator. In a feed-forward path, frequency dividers divide a high frequency signal from the oscillator to a lower desired frequency, thereby increasing phase resolution.

REFERENCES:
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patent: 2005/0251775 (2005-11-01), Wood
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Savoj, et al. “A 10-Gb/s CMOS clock and Data Recovery Circuit With a Half-Rate Binary Phase/Frequency Detector”, IEEE Journal of Solid-State Circuits vol. 38 No. 1, Jan. 2003, pp. 13-21.

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