Phase lock loop used as up converter and for reducing phase...

Details Phase lock loop used as up converter and for reducing phase... Phase lock loop used as up converter and for reducing phase...

1999-09-27

2001-07-03

Grimm, Siegfried H. (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

With reference oscillator or source

C332S103000, C332S144000, C375S302000, C375S308000

Reexamination Certificate

active

06255912

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates, generally, to communication systems and processes which use phase lock loops, and, in particular embodiments, to systems and processes which use phase lock loops as translation loops in the process of modulation.
2. Description of Related Art
It has become increasingly important to minimize the cost of various electronic devices, especially personal communication devices such as cellular telephones, cordless telephones, and the like. One way to minimize the cost of such devices is to minimize the number of components and functions required in the electronic device. Another way to miniimize cost is to use the same component to perform different functions in different applications. Personal communication devices, however, often require complex circuitry with a number of components for performing particular functions. This is especially true in modern cellular phone communications.
One of the circuits that has been particularly useful in communications electronics is the Phase Lock Loop (PLL). A phase lock loop (PLL) circuit is a circuit that is used for the synchronization of signals. Phase lock loops are used in a wide variety of electronic circuits, in which signals, containing analog and digital information, are decoded. Phase lock loops may be thought of as synchronizing circuits, in which an output frequency is synchronized, or locked, to a reference frequency. PLLs are also used in mobile communication applications related to such purposes as frequency generation, signal modulation, signal demodulation, data decoding and data encoding.
PLLs are unsynchronized when they have no reference signal. In the unsynchronized condition PLLs are said to be unlocked, or out of lock. Phase lock loops generally work by comparing a reference frequency to a generated output frequency and adjusting the output frequency to match the reference frequency. As the output signal is adjusted by the loop, there occurs a point, at which the frequencies of the output and reference signals match. At the point, that frequencies of the output and reference signals match, the signals are sometimes said to be in frequency lock. When the generated frequency is further synchronized in phase with the input frequency, the frequencies are commonly said to be in phase lock, the locked state, or simply lock. During lock, when the output frequency is synchronized with the reference frequency, the phase error, between the output frequency and reference frequency, may be very small or even zero. The output signal will generally stay in the lock state until the phase lock loop is somehow perturbed.
Phase lock loops have application not only in frequency synchronization, but also in frequency synthesis, and frequency generation. PLL's may incorporate divider, multiplier, or mixer circuits in order to create lower, higher, or translated frequencies.
Even though the practice of translating frequencies can be accomplished by phase lock loops, translating frequencies can also be accomplished by mixer circuits. Mixer circuits can inject noise into the system which must be then attenuated using filters or other means. Noise within these circuits can be problematical and degrade circuit performance. Current mixer circuits and PLL translation circuits, are not helpful in attenuating circuit noise and may even inject further noise to these circuits.
SUMMARY OF THE DISCLOSURE
A characteristic of phase lock loops is that they have loop bandwidth which has direct influence on design parameters like settling time, pull in, phase noise, etc. That is they can synchronize signals within a range that constitutes their bandwidth. This limited bandwidth can be tailored to individual applications. As a consequence of having a limited bandwidth, phase lock loops possess filtering characteristics and can also be used as filters since they reject signals that are not within their bandwidth, and can filter noise which is within their bandwidth.
In addition, phase lock loops can be used to translate frequencies. Phase lock loops, that are used to translate frequencies, are commonly referred to as translation loops. The use and functioning of translation loops is known in the art, and discussed, for example, in “Microwave and Wireless Synthesizers” by Ulrich L. Rhode 1997 which is incorporated by reference herein. Using a translation phase lock loop, the output frequency, which can be the broadcast frequency of a device such as a portable phone, can be mixed with a translation frequency. By choosing the translation frequency, the translated signal, resulting from the mixing of the broadcast frequency and the translation frequency, can be the same frequency as the signal input into the phase lock loop. If the signal into the phase lock loop is a phase modulated signal, such as the phase portion of a PSK signal, the phase modulated signal is thereby translated into the broadcast frequency by the phase lock loop. In other words by having a translation occur, within the phase lock loop, a phase modulated signal can be input into the loop and a broadcast frequency can be the output of the loop. By using a phase lock loop to translate frequencies, the ability of the loop to reject noise present within the loop bandwidth can be used to reduce the phase noise of components placed within the loop. If the reference signal of the phase lock loop has low phase noise the phase lock loop essentially cleans up pull in noise within the loop bandwidth. The loop bandwidth needs to be determined such that it is wide enough to cancel phase noise and track a phase modulated reference signal.
For example, a translation phase lock loop can be used to generate a transmit frequency that is then provided to an amplitude modulator. If, however, the amplitude modulator is included within the phase lock loop, the filtering properties of the loop can reduce the phase noise, that is created in the amplitude modulator. The noise reduction created by including the amplitude modulator within the phase lock loop is essentially free, because both components are present in the communication system regardless of their placement. A benefit, of noise reduction, comes from rearranging the components, so that the power amplifier can benefit from the filtering that is present within the phase lock loop. The amplitude modulator, mentioned in the previous example, is used for illustration purposes only. Any signal modifying circuit could be placed within the loop and the loop would tend to remove any phase noise, that is introduced by that circuit. For examples such circuits may be amplifiers, amplitude modulators, power amplifiers, or other circuits.
The disclosure focuses on embodiments wherein a R, &thgr; translational loop generates complex band limited Phase Shift Keying (PSK) signals. These signals have amplitude modulation (AM) along with phase modulation and hence traditionally needed linear amplification.
Embodiments of the invention exploit the properties of a phase lock loop by utilizing a novel architecture to achieve power generation of such signals by canceling phase noise which may be generated in circuits such as the AM modulators.
This and other objects, features, and advantages of embodiments of the invention will be apparent to those skilled in the art from the following detailed description of embodiments of the invention, when read with the drawings and appended claims.


REFERENCES:
patent: 4528526 (1985-07-01), McBiles
patent: 4831339 (1989-05-01), Nemeth
patent: 5233314 (1993-08-01), McDermott et al.
patent: 5909149 (1999-06-01), Bath et al.
patent: 6005443 (1999-12-01), Damgaard et al.

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