Telecommunications – Transmitter and receiver at same station – With frequency stabilization
Reexamination Certificate
1998-08-31
2001-02-20
Tsang, Fan (Department: 2746)
Telecommunications
Transmitter and receiver at same station
With frequency stabilization
C455S084000, C455S180200, C455S260000
Reexamination Certificate
active
06192220
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a method of providing ultrafast lock times in half duplex time division multiple access wireless data application.
BRIEF DESCRIPTION OF THE PRIOR ART
Communication worldwide presently utilizes a system known as Global System of Mobile Communications (GSM) which is a worldwide standard. At present, this system is being used mainly for voice applications, however, it is expected that this system will be used increasingly, in the future, for data transmission and reception as well. The GSM system utilizes time division multiple access (TDMA) wherein each frequency channel is divided up into a plurality of time slots with each user operating at a particular frequency and in a particular time slot at a given window of time. To switch from channel to channel, it is necessary that the frequency of the mobile device change, this frequency change being provided by changing the frequency of operation of the main oscillator at the mobile device which is generally a voltage controlled oscillator (VCO). The frequency provided by the VCO must be moved very accurately and is moved under control of a reference to a crystal oscillator within the device. The mechanism which controls this change in frequency is known as a phase lock loop (PLL) or frequency synthesizer.
In half duplex operation, the device is either transmitting or receiving, but not both simultaneously. Since transmission and reception are at different frequencies known to the device as determined by the base station, it is necessary that the system cease operation or go to sleep for a short period of time while the oscillator frequency is changed from the transmit mode frequency to the receive mode frequency and vice versa. This is known as “set up time”, the set up time required being known at the base station so that transmission from the base station to the mobile device will not start from the time of request for transmission until the set up time has elapsed. This set up time for GSM is presently about 600 microseconds. The set up or switching time (the time for the oscillator to switch from the receive frequency to the transmit frequency and settle down to the switched frequency) required for a switch from reception from to transmission to the base station can be up to about two such time slots because the mobile device must wait for its time slot to arrive in addition to the time required for the frequency change. In addition, there is a problem of worsened system phase noise and feed-through spur suppression as a result of faster switching time. A tradeoff is required among these parameters since compensation for one will adversely affect the others.
The present technology in wireless phase lock loop systems is either an integer N or fractional N synthesizer used to lock the voltage controlled oscillator (VCO) of the system to the desired frequency. In the current standard approach, the fractional N synthesizer is used for applications where faster switching times are required. However, in order to obtain the increased bandwidth which is required for data transmission, the transmit and receive cycles will occupy several consecutive time slots rather than single time slots periodically spaced from each other. Also, less set up time will be allowed to save space in the time domain as well as to meet expected new standards. Accordingly, the next generation of GSM systems will require a lock time of about 100 to 120 microseconds between the receive and transmit functions. This lock time is either beyond the ability of state of the art fractional N architecture or requires architecture which is always in condition to accommodate the fastest expected switching time and therefore constantly suffers from the problems of worsened system phase noise and feed through spur suppression as discussed above whereas the improved lock time is generally required for only a small percentage of the total transmission time utilized by the mobile device, thereby seriously diminishing the performance of the system when the fast lock time is not required. It follows that a new improved architecture is required.
SUMMARY OF THE INVENTION
In accordance with the present invention, the above described problem inherent in the prior art is overcome and there is provided a phase lock loop system capable of operation in about the 120 microsecond time frame.
Briefly, the above is accomplished by taking advantage of a prior art direct digital synthesizer (DDS) in conjunction with a traditional synthesizer. DDSs are well known and provide a stable step output wave of predetermined type which is then filtered to provide an output smooth sine wave which is up to one half of the frequency of a stable reference input to the DDS. For most wireless applications presently required, DDS is presently not a viable alternative for wireless applications. DDSs at present can only provide output frequencies up to about 300 to 400 MHz and in any event less than 500 MHz, which is inadequate for most wireless systems and especially commercial wireless systems. For example, GSM operates at frequencies in the range of 880 to 960 Mhz., it being understood that the present invention is not limited to GSM In addition, a DDS consumes very large amounts of power and has limited frequency range. This makes the use of the DDS alone impractical for mobile systems due to the enormous battery drain required for operation.
The approach used in accordance with the present invention to overcome these limitations of a DDS is to use, during normal operation for a Global System of Mobile Communications (GSM) or TDMA telephone (a well known digital communication system), a traditional integer N or fractional N synthesizer to switch the VCOs to the desired frequency. However, when the telephone goes into the data mode or some other mode that requires the wireless application to change its operating frequency from transmit to receive and/or vice versa, such as, for example, within about 120 microseconds of each other, the DDS approach is used in place of the traditional integer or fractional N synthesizer. A DDS requires programming and an input clock frequency. The programming comes from the digital signal processor (DSP) in the telephone and the clock frequency is the locked intermediate frequency (IF) VCO. This ensures that the DDS is phase locked with the rest of the system.
The system in accordance with the present invention requires a very careful frequency plan for the radio to take into consideration the frequency range limitation of the DDS and also that the DDS would require clocking with the IF VCO. A consideration of output spurs from the mixed output of the DDS and the IF VCO is critical. The lock-detect pin on the PLL chip, which is well known prior art technology, is designed to drive the necessary additional switches when the PLL has reached the lock state. The careful switching approach between the locked VCO and the DDS and IF VCO output is crafted to stop any phase glitches between the two signals. The four required switches are designed to be fast and low loss. This implementation requires a DDS circuit as well as an additional mixer and filter.
For operation of the system in accordance with the present invention, initially, the PLL is operating at the receive frequency using the traditional PLL synthesizer of the prior art. When the mobile unit is to go into the data transmission mode, the DDS is tuned to the correct frequency for transmission with reception being terminated and, simultaneously, the PLL is commenced to be tuned to the correct transmit frequency. After the 120 microsecond set up time has elapsed, transmission is commenced using the DDS and then, when the PLL has stabilized at the transmit frequency, such as, for example, after 400 to 600 microseconds, the PLL takes over and the DDS is turned off. In this way, the DDS is used only when the 120 second set up time is required and, even then, is used only until the PLL has stabilized and is able to take over the function of providing the required operating frequ
Henwood Andrew M.
Ruiz Everardo D.
Brady III Wade James
Neerings Ronald O.
Sobutka Philip J.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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