Oscillators – Automatic frequency stabilization using a phase or frequency... – Tuning compensation
Reexamination Certificate
2008-05-13
2008-05-13
Lee, Benny T. (Department: 2817)
Oscillators
Automatic frequency stabilization using a phase or frequency...
Tuning compensation
C331S011000, C331S025000, C331SDIG002, C327S157000
Reexamination Certificate
active
07372339
ABSTRACT:
A phase-locked loop (PLL) circuit includes a power-on-reset (POR) to reset a digital block and set an initial input voltage value VCTRL of voltage-controlled oscillator (VCO). An input divider and a feedback divider are provided to set the frequency ratio of output to input and to raise the resolution of the output frequency. First and second phase frequency detectors are used to measure the phase difference between the two input signals and generate a pulse corresponding to the phase difference. First and second reducing dividers are inserted before the first and second phase frequency detectors to decrease the input frequency of the respective phase frequency detector and keep the ratio of the input frequency and natural frequency (Wn) as a constant. A lock-state detector is used to detect whether the PLL is locked or unlocked. A charge pump is used to provide charge signals corresponding to the pulse. A loop filter is coupled to the output node of the charge pump to provide a voltage VCTRL responding to the charge signals.
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Johnson Ryan J
Lee Benny T.
Semiconductor Manufacturing International (Shanghai) Corporation
Townsend and Townsend / and Crew LLP
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