Phase lock loop for data decoder clock generator

Details Phase lock loop for data decoder clock generator Phase lock loop for data decoder clock generator

1977-01-28

1979-12-25

Safourek, Benedict V.

Telegraphy

Systems

Line-clearing and circuit maintenance

358 4, H04L 702

Patent

active

041807014

ABSTRACT:
Apparatus is disclosed for phase locking the output of a voltage controlled oscillator to a self-clocking data pulse stream occurring at a basic predetermined rate, the data stream being of the kind in which the data content is determined by a signal state change located in one of two positions within the data cell interval of the data stream. Each signal state change is defined by a narrow data pulse. The oscillator is controlled by a first means to operate at the predetermined rate when the data pulses are not present and by a second means when the data pulses are present. The second means compares one selected transition of the clock pulses of the oscillator output signal to the position of the data pulse and provides a variable control voltage to the oscillator to adjust its phase so that the the selected clock pulse transition is synchronized to occur at the midpoint of the data pulses.

REFERENCES:
patent: 3896265 (1975-07-01), Hard et al.
patent: 3991378 (1976-11-01), Schaefer

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