Phase lock loop destress circuit

Details Phase lock loop destress circuit Phase lock loop destress circuit

2001-11-01

2003-11-04

Pascal, Robert (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Tuning compensation

C331S017000, C331S025000

Reexamination Certificate

active

06642799

ABSTRACT:

TECHNICAL FIELD
The present invention generally relates to microelectronic devices. More particularly, the present invention relates to phase lock loop circuits including loop destress logic that automatically selects an appropriate coarse setting based on a control setting under lock.
BACKGROUND OF THE INVENTION
Phase lock loop (PLL) circuits are often employed to generate stable output frequency signals from a fixed, low frequency signal. Such circuits are often employed in receivers, transceivers, frequency multipliers, and frequency demodulators.
Traditional PLL circuits generally include a phase detector, a charge pump, a loop filter, and a voltage controlled oscillator (VCO). In operation, the phase detector receives a reference signal and a signal from the output of the PLL, compares the phase difference of the signals and produces an error current pulse signal indicative of the difference in phase, the loop filter converts the current pulse signal to a direct current voltage level, and the VCO adjusts its oscillation frequency based on the control voltage received from the filter until the error between the output signal from the PLL circuit and the reference frequency is near zero, i.e., the signals are “locked” to each other.
The control voltage from the filter is often limited by the chip power supply to a maximum range of about to about two to five volts, which corresponds to the range of output frequencies from the VCO. In other words, the frequency of VCO can be manipulated from its low frequency to its high frequency by adjusting the input control voltage to the VCO over a range of about two to five volts. In this case, very small changes in voltage lead to large changes in VCO output frequencies. Consequently, electronic noise in or proximate the PLL circuit may undesirably cause large changes in the output frequency of the PLL circuit.
To reduce a sensitivity of VCO frequency to input control voltage, conventional PLL circuits may include digital tuning architecture. For example, the PLL circuit may include coarse-tuning architecture that uses a digital word to facilitate tuning of the PLL. Such conventional tuning circuitry typically requires preselection of a digital word which limits an overall operating frequency of the VCO. Although preselection of the digital word facilitates tuning of the PLL, such preselection may not allow for optimal tuning of the PLL. Accordingly, improved PLL circuits with digital tuning architecture are desired.
SUMMARY OF THE INVENTION
The present invention provides an improved phase lock loop circuit. More particularly, the invention provides a PLL circuit that uses digital logic for coarse tuning of the PLL circuit.
The way in which the present invention addresses the drawbacks of the now-known PLL circuits is discussed in greater detail below. However, in general, the invention provides an improved PLL circuit that is capable of selecting a word for use in tuning the circuit, wherein the word is selected based on an amount of change desired in the operating frequency of the VCO.
In accordance with one embodiment of the invention, a PLL circuit includes an integrator, a summer and driver, a voltage controlled oscillator, and a loop destress logic circuit and a coarse tune digital-to-analog converter coupled between the integrator and the summer and driver.
In accordance with one aspect of the invention, the voltage controlled oscillator includes a look-ahead interpolation architecture to further facilitate tuning of the VCO.
In accordance with a further embodiment of the invention, the PLL circuit includes a differential voltage to current translator to generate control voltages for a portion of the VCO.
In accordance with a further embodiment of the invention, the coarse tune digital-to-analog converter is a current output digital-to-analog converter. In accordance with one aspect of this embodiment, the digital-to-analog converter is an eight bit converter.
In accordance with a further embodiment of the invention, the integrator includes a differential output operational amplifier. In accordance with one aspect of this embodiment, the integrator also includes two feedback loops, each including a capacitor and a resistor.
In accordance with yet another embodiment of the invention, the PLL circuit includes two comparators for providing input to the coarse tune digital-to-analog converter, wherein the input provided is indicative of a desired coarse tune adjustment.


REFERENCES:
patent: 5600321 (1997-02-01), Wincn
patent: 5604465 (1997-02-01), Farabaugh
patent: 5847616 (1998-12-01), Ng et al.
patent: 5977898 (1999-11-01), Ling et al.
patent: 6188739 (2001-02-01), Everitt et al.
patent: 6300831 (2001-10-01), Xi

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