Phase lock loop data timing recovery circuit

Details Phase lock loop data timing recovery circuit Phase lock loop data timing recovery circuit

1977-09-06

1979-12-25

Grimm, Siegfried H.

Oscillators

Automatic frequency stabilization using a phase or frequency...

Plural oscillators controlled

331 23, 331 25, H03B 304

Patent

active

041807839

ABSTRACT:
A phase locked loop including a voltage-controlled oscillator and a divider is used to derive a clock timing signal from a received data stream having a given bit transmission rate. The divider may be programmable so that the circuit can derive a clock from a data stream having any one of a plurality of integrally-related bit rates. A second phase locked loop (having a second programmable divider) is inserted in the feedback path to permit clock recovery from data streams having fractionally-related bit rates.

REFERENCES:
patent: 2627033 (1953-01-01), Jensen et al.
patent: 3354403 (1967-11-01), Thomas
patent: 3769602 (1973-10-01), Griswold

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