Oscillators – Automatic frequency stabilization using a phase or frequency... – Particular error voltage control
Reexamination Certificate
2000-03-02
2001-11-20
Kinkead, Arnold (Department: 2817)
Oscillators
Automatic frequency stabilization using a phase or frequency...
Particular error voltage control
C327S157000, C327S112000, C327S536000
Reexamination Certificate
active
06320470
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a phase lock loop circuit (hereafter referred to as a “PLL”) formed on an integrated circuit, and more specifically, it relates to a loop filter (hereafter referred to as an “LPF”) thereof.
2. Description of the Related Art
A PLL is a circuit that causes the phase of an output signal from an oscillator to conform to the phase of a reference signal provided from the outside. PLLs are employed in a wide range of applications including frequency synthesizers that generate a signal at an arbitrary frequency based upon the frequency of a reference signal and a clock reproduction circuit that extracts a synchronous clock signal from a data signal.
FIG. 2
is a block diagram of a PLL in the prior art.
This PLL comprises a phase difference detection circuit (hereafter referred to as a “PFD”)
1
, a voltage controlled oscillator circuit (hereafter referred to as “VCO”)
2
, a feedback circuit
3
and an LPF
10
.
The PFD
1
detects the difference between the phases of a reference signal FR and an internal signal FI, and it outputs a detection signal UP by setting the level of the corresponding signal to “L” if the phase of the internal signal FI is retarded relative to the reference signal FR, whereas it outputs a detection signal DN by setting the level of the corresponding signal to “L” if the phase of the internal signal FI is advanced relative to that of the reference signal FR, shifting the phase to a degree corresponding to the length of time that represents the phase difference. If there is no phase difference, the PFD
1
outputs detection signals UP and DN with their levels set to “H.”
The LPF
10
generates a stable control voltage VC, which corresponds to the phase difference by suppressing the high frequency component of the detection signal UP or DN. The LPF
10
is provided with a P-channel MOS transistor (hereafter referred to as a “PMOS”)
11
, connected between a source potential VDD and a node N
1
on which ON/OFF control is implemented by the detection signal UP provided by the PFD
1
. In addition, the LPF
10
is provided with an inverter
12
that inverts the level of the detection signal DN and an N-channel MOS transistor (hereafter referred to as an “NMOS”)
13
, which is connected between a ground potential GND and a node N
1
and whose ON/OFF state is controlled by an output signal from the inverter
12
. One end of a resistor
14
is connected to the node N
1
, with the other end of the resistor
14
connected to a node N
2
. A resistor
15
and a capacitor
16
, which are connected in series, are connected between the node N
2
and the ground potential GND, and the resistors
14
and
15
and the capacitor
16
constitute a lag lead filter. In addition, the control voltage VC, with the high frequency component and noise removed, which corresponds to the phase difference is output through the node N
2
.
The VCO
2
, which is an oscillator that controls the frequency of an oscillation signal FV that it outputs based upon the control voltage VC, achieves characteristics whereby, for instance, the frequency of the oscillation signal FV is caused to increase in correspondence to a rise in the control voltage VC. In addition, the feedback circuit
3
, which may be constituted of, for instance, a frequency divider, divides the frequency of the oscillation signal FV into 1
and outputs the divided frequency as the internal signal FI to the PFD
1
.
Now, the operation achieved in the PLL in the prior art structured as described above is explained by using an example in which the VCO
2
is set to oscillate over a specific frequency range with the center of the range at 1 MHz and the frequency division ratio at the feedback circuit
3
set at 1/10.
First, when the power is turned on at the PLL, a reference signal FR with its frequency at, for instance, 100 kHz is provided from the outside.
Immediately after the power up, when the capacitor
16
at the LPF
10
has not yet been charged, the control voltage VC output by the LPF
10
is low and the frequency of the oscillation signal FV output by the VCO
2
is lower than 1 MHz. Consequently, the frequency of the internal signal FI output by the feedback circuit
3
is lower than 100 kHz, causing the phase of the internal signal FI to be retarded relative to the phase of the reference signal FR, which results in a detection signal UP at “L” output from the PFD
1
. This detection signal UP at “L” turns on the PMOS
11
, thereby causing a current to flow from the source potential VDD into the capacitor
16
via the PMOS
11
, the resistor
14
and the resistor
15
to charge the capacitor
16
. As a result, the control voltage VC output through the node N
2
of the LPF
10
rises.
The rise in the control voltage VC causes the frequency of the oscillation signal FV output by the VCO
2
to increase. Then, when the oscillation signal FV achieves a frequency of 1 MHz and the frequency of the internal signal FI reaches 100 kHz to achieve a phase lock, the levels of the detection signals UP and DN output by the PFD
1
are both set to “H.” This causes the LPF
10
to stop the rise of the control voltage VC that it outputs to hold the control voltage VC at a constant value. Thus, the frequency of the oscillation signal FV output by the VCO
2
is fixed at 1 MHz.
In this PLL, if, for instance, a fluctuation in the source voltage causes the phase of the internal signal FI to advance relative to the phase of the reference signal FR, the PFD
1
outputs a detection signal DN with its level set to “L” to turn on the NMOS
13
at the LPF
10
. When the NMOS
13
is turned on, the electrical charge stored at the capacitor
16
is discharged to the ground potential GND via the resistors
15
and
14
and the NMOS
13
, resulting in a fall in the control voltage VC output through the node N
2
of the LPF
10
. This fall in the control voltage VC causes the frequency of the oscillation signal FV output by the VCO
2
and the frequency of the internal signal FI output by the feedback circuit
3
to decrease as well. As a result, the phase of the internal signal FI is retarded until there is no phase difference relative to the phase of the reference signal FR.
If, on the other hand, the phase of the internal signal F
1
is retarded relative to the phase of the reference signal FR, the PFD
1
outputs a detection signal UP with its level set to “L” to raise the control voltage VC output from the LPF
10
. This rise in the control voltage VC causes the frequency of the oscillation signal FV output by the VCO
2
and the frequency of the internal signal FI output by the feedback circuit
3
to increase as well. As a result, the phase of the internal signal FI advances until there is no phase difference relative to the phase of the reference signal FR.
As explained above, the PLL in the prior art is structured so that it engages in operation during which the phase of the internal signal FI is made to conform to the phase of the reference signal FR through feedback control.
The response characteristics of the LPF
10
, which generates the control voltage VC based upon the detection signals UP and DN greatly affect the operating characteristics of the PLL. Namely, while setting the time constant at the lag lead filter constituted of the resistors
14
and
15
and the capacitor
16
at a large value results in an increase in the length of time elapsing until the phase lock is achieved (the lockup time), the phase jitter, caused by noise and the like, is minimized once the phase lock is achieved. If the time constant at the lag lead filter is set at a small value, on the other hand, the lockup time is reduced, but the phase jitter due to noise and the like increases.
A PLL that includes an LPF having a time constant set at a large value is employed in, for instance, a clock reproduction circuit to reduce phase jitter in the prior art. In addition, a PLL that includes an LPF having a small time constant is employed in frequency synthesizers utilized for transm
Arai Kenji
Yokoyama Tomonobu
Kinkead Arnold
Kunitz Norman N.
OKI Electric Industry Co., Ltd.
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