Phase lock loop circuit using signal estimator

Details Phase lock loop circuit using signal estimator Phase lock loop circuit using signal estimator

1999-12-03

2001-09-25

Grimm, Siegfried H. (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

With intermittent comparison controls

C331S025000, C455S296000

Reexamination Certificate

active

06294960

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to a phase lock loop circuit which, in communication systems for digital transmission, detects and corrects a phase shift, in a received signal, attributable, for example, to a phase variation created in frequency offset or signal rise in burst transmission, and more particularly to a phase lock loop circuit using a signal estimator, which can accurately detect and correct a phase shift even in the case of a received signal which has been remarkably deteriorated by transmission path distortion.
BACKGROUND OF THE INVENTION
In communication systems for digital transmission, a signal received by a receiver often contains a phase attributable, for example, to a phase variation created in frequency offset or signal rise in burst transmission. A phase lock loop circuit is provided on the receiver side in order to detect and correct the phase shift contained in the received signal.
Further, for communication systems for digital transmission, the received signal is influenced by distortion created in the transmission path. Therefore, in order to restore the received signal which has been deteriorated by the transmission path distortion, an equalizer or a signal estimator is provided on the receiver side.
To this end, a phase lock loop circuit using a signal estimator is provided on the receiver side in communication systems for digital transmission to remove the transmission path distortion and, at the same time, to correct the phase shift.
The construction of a conventional phase lock loop circuit using a signal estimator described in Japanese Patent Application No. 135454/1997 will be described with reference to
FIG. 1
(block diagram).
This conventional phase lock loop circuit using a signal estimator comprises a phase rotator
102
, a delay element
120
, a signal estimator
303
, a replica generator
112
, a phase detector
113
, a filter
114
, and VCO (a voltage controlled oscillator)
115
.
The phase rotator
102
rotates the phase of a received signal
117
input through an input terminal
101
based on a signal generated by VCO
115
to correct the phase shift contained in the received signal
117
.
The signal estimator
303
estimates a transmission signal series from the distorted received signal by a Viterbi algorithm, and outputs an estimated signal
116
.
The replica generator
112
performs a convolution operation of a previously determined transmission path impulse response value and the estimated signal
116
estimated by the signal estimator
303
to generate a replica signal
118
of the received signal
117
which is then output.
The phase detector
113
detects the phase difference between the replica signal
118
generated in the replica generator
112
and a signal output from the delay element
120
. In this case, when the received signal
117
involves a frequency offset, the phase between the transmitted signal and the received signal changes with the elapse of time. This leads to a change in phase difference detected by the phase detector
113
with the elapse of time.
In the replica generator
112
, the transmission path impulse response value used in the convolution operation is constant. Therefore, the replica signal
118
is output which does not suffer from phase variation so far as any error does not occur in the signal estimator
303
. Since, however, the output signal of the delay element
120
suffers from a phase change, this phase difference is output from the phase detector
113
.
The delay element
120
outputs the signal output from the phase rotator
102
by the quantity of delay equal to that created in the signal estimator
303
. This permits the timing of the replica signal
118
output from the replica generator
112
to be synchronized with the timing of the signal output from the delay element
120
.
The filter
114
filters the phase difference detected by the phase detector
113
, and then outputs the bandwidth-limited VCO
115
.
VCO
115
outputs a signal, of which the frequency is controlled by the signal output from the filter
114
, to the phase rotator
102
.
In this case, the phase detector
113
, the filter
114
, VCO
115
, the phase rotator
102
operates as feedback loop means.
Next, the operation of this conventional phase lock loop circuit using an signal estimator will be explained.
The phase of the phase shift-containing received signal
117
input through the input terminal
101
is rotated by the phase rotator
102
, and the signal is then input into the delay element
120
and the signal estimator
303
. At the beginning of the operation of the phase lock loop circuit, a signal output from the phase rotator
102
contains a phase shift.
In the signal estimator
303
, a transmission signal series is estimated from the phase-rotated received signal using Viterbi algorithm, and the signal estimator
303
outputs the estimate signal
116
. The delay element
120
delays the signal output from the phase rotator
102
by the quantity of delay equal to that created in the signal estimator
303
, and then outputs the delayed signal.
The phase detector
113
detects the phase difference between the replica signal
118
generated in the replica generator
112
and the signal output from the delay element
120
. The phase difference detected by the phase detector
113
is bandwidth limited by the filter
114
, and then input, as information on phase difference to be corrected, into VCO
115
. The signal output from VCO
115
is input into the phase rotator
102
, where the phase of the received signal
117
is rotated to correct the phase shift contained in the received signal
117
.
In this conventional phase lock loop circuit using a signal estimator, control is performed toward a reduction in phase difference detected by the phase detector
113
. Thus, the phase shift attributable, for example, to frequency offset contained in the received signal
117
is absorbed.
In this conventional phase lock loop circuit using a signal estimator, a phase error signal in the phase lock loop operation is generated from the series signal estimated in the signal estimator
303
using the replica signal
118
. Therefore, phase lock correcting operation can be done with high accuracy even in the case of a received signal having large transmission path distortion.
In deciding the estimated signal in the conventional Viterbi algorithm, the so-called “traceback” is carried out wherein a decision is made in such a manner that the smallest path is selected among path metric values and traceback is then performed by a certain number from this path (for example, by 10 symbols) to determine the status of the path. The estimated signal
116
is output as a result of the decision.
In the conventional phase lock loop circuit using a signal estimator shown in
FIG. 1
, due to the constriction thereof, establishment of the estimated value by the series estimation in the signal estimator
303
causes some time delay. When the phase change rate is small, operation is performed without any problem even though the delay derived from the signal estimation in the signal estimator
303
is large. On the other hand, when the phase change rate has become large at the time of initial pulling or the like, the phase follow-up of the phase lock loop cannot catch up with the phase change, leading to divergence.
One method for increasing the phase follow-up speed of the phase lock loop is such that the frequency band of the filter
114
shown in
FIG. 1
is broadened to increase the response speed of the phase lock loop. Broadening the frequency band of the filter
114
, however, is likely to be influenced by disturbance such as noise. This deteriorates the follow-up accuracy of the phase shift.
Another method for increasing the phase follow-up speed of the phase lock loop is to decrease the estimation delay time of the signal estimator
303
, thereby increasing the response speed. Decreasing the delay of the signal estimator
303
, however, decreases the estimation ability of the signal estimator
303
. Therefore, the estim

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