Phase lock loop circuit for signals periodically inverting in ph

Details Phase lock loop circuit for signals periodically inverting in ph Phase lock loop circuit for signals periodically inverting in ph

1994-01-21

1995-07-25

Pascal, Robert J.

Oscillators

Automatic frequency stabilization using a phase or frequency...

Plural a.f.s. for a single oscillator

331 1A, 331 14, 331 17, H03L 706

Patent

active

054365988

ABSTRACT:
A phase lock loop (PLL) circuit which includes an input for inputting an incoming signal which is to be tracked, a phase lock loop subcircuit, a phase state indicator subcircuit, and a synchronized blanking window generator. These elements create a phase lock loop circuit capable of producing a stable output which closely tracks the incoming signal, even when the incoming signal shifts in phase by 180 degrees. The phase state indicator subcircuit detects a phase reversal in the incoming signal and outputs a signal indication such. This indicating signal is used by the phase lock loop subcircuit to produce a stable reference signal tracking the incoming signal most of the time. However, during a short period of time between the inversion of the incoming signal and the output of the indicating signal by the phase state indicator subcircuit, the synchronized blanking window generator provides a signal to the phase lock loop subcircuit which is used to stabilize the reference signal.

REFERENCES:
patent: 4400667 (1983-08-01), Belkin
patent: 4787097 (1988-11-01), Rizzo
patent: 5170135 (1992-12-01), Ito et al.

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