Phase-lock-loop circuit and method for compensating, data bias i

Details Phase-lock-loop circuit and method for compensating, data bias i Phase-lock-loop circuit and method for compensating, data bias i

1992-09-30

1993-10-19

Grimm, Siegfried H.

Oscillators

Automatic frequency stabilization using a phase or frequency...

Plural a.f.s. for a single oscillator

331 16, 331 36C, 331177V, 331DIG2, 332102, 332128, 332136, 375 66, 375120, H03L 7099, H03L 7189, H03L 2712, H04L 2712

Patent

active

052549585

ABSTRACT:
Biomedical information is directly digitally telemetered from the patient through a frequency modulated transmitter to a remote receiver and computer station. A phase-lock-loop circuit in the digital transmitter compensates for DC data bias by averaging and generating a scaled measure of the DC content of the digital data fed into the phase-lock-loop circuit. The average signal is then provided as a control signal to a first voltage controlled crystal oscillator, the output of which is then used as a reference frequency for the phase-lock-loop circuit. Frequency modulation of the digital data is provided by coupling the digital data directly into the voltage control input of the voltage controlled oscillator which generates the output frequency. Further control of the phase-lock-loop circuit in the transmitter is achieved by prepositioning the operating frequency of the voltage controlled oscillator by means of a microcontroller. The input to the microcontroller is a digital word corresponding to the desired frequency. The microcontroller then uses an algorithm to set the operating frequency of the voltage controlled oscillator at a preselected point within the bandwidth of the phase-lock-loop circuit. The operating point of the phase-lock-loop circuit is set by a first varactor diode while fine tuning of the voltage controlled oscillator is provided by a second varactor diode. The operating point of the voltage controlled oscillator is set in such a position of the tuning curve of the voltage controlled oscillator that the gain of the oscillator approximately compensates for any changes in the dividing integer used in a divider in the phase-lock-loop circuit.

REFERENCES:
patent: 3622913 (1971-11-01), Shipley
patent: 4074209 (1978-02-01), Lysobey
patent: 4513448 (1985-04-01), Maher
patent: 4847569 (1989-07-01), Dudziak et al.

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