Phase lock loop circuit

Details Phase lock loop circuit Phase lock loop circuit

2011-05-31

2011-05-31

Kinkead, Arnold (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Tuning compensation

C331S179000, C331S034000, C331S00100A, C327S156000, C327S159000

Reexamination Certificate

active

07952436

ABSTRACT:
A phase lock loop (PLL) circuit is provided. A voltage controlled oscillator (VCO) generates an output clock signal based on a control voltage. A controller provides a first digital control word, a second digital control word and a loop factor. A frequency modifier is coupled to the output clock signal, controlled by the controller to divide the output clock signal by the loop factor to generate a feedback frequency. A charge pump is controlled by the up signal and down signal to generate a charge pump current, comprising a first digital to analog converter (DAC) to generate a first current based on the first digital control word when the up signal is asserted. A second DAC generates a second current based on a second digital control word when the down signal is asserted. The controller defines a first relationship between the first digital control word and the loop factor, and the controller defines a second relationship between the second digital control word and the loop factor.

REFERENCES:
patent: 6724265 (2004-04-01), Humphreys
patent: 6911868 (2005-06-01), Kumar DVJ
patent: 7106141 (2006-09-01), Puma

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