Oscillators – Automatic frequency stabilization using a phase or frequency... – Particular error voltage control
Reexamination Certificate
1999-07-02
2002-03-12
Mis, David (Department: 2817)
Oscillators
Automatic frequency stabilization using a phase or frequency...
Particular error voltage control
C331S008000, C331S010000, C331S011000, C327S062000, C327S111000, C327S147000, C327S148000, C327S156000, C327S157000, C375S376000, C455S260000
Reexamination Certificate
active
06356160
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to clock recovery and in particular the present invention relates to automatic gain control circuitry for recovering a clock from high data rate signals.
BACKGROUND OF THE INVENTION
Clock and data recovery in high speed data communication systems require receiver circuits which can adjust an internal oscillator to a frequency and phase of the communicated data. For a description of clock recovery, see C. R. Hogge, “A Self Correcting Clock Recovery Circuit,” IEEE, J. Lightwave Technol. LT-3 1312 (1985). Hogge describes a receiver circuit which adjusts a recovered clock signal to center the clock signal transitions in a center of the communicated data signal.
The receiver circuits typically require a phase lock loop circuit to acquire the clock signal from the transmitted data. Phase lock loop circuits adjust an internal oscillator to match a phase of an externally supplied reference signal, such as the received data signal. These phase lock loop circuits compare the reference signal to the internal oscillator signal and provide an output which is used to adjust the oscillator. For example, a parallel digital phase lock loop architecture is described in Fiedler et al., “A 1.0625 Gbps Transceiver with 2x-Oversampling and Transmit Signal Pre-Emphasis,” ISSCC 1997 Dig. Tech. Papers, 238 (1997).
High speed data recovery in a communication system operating in excess of 1 GHz requires high speed components, a speed which is difficult to achieve in complementary metal oxide semiconductor (CMOS) fabrication. In particular, current CMOS fabrication sizes of about 0.18 to 0.35 micron have NMOS transistors with a frequency cutoff f
t
of about 10 to 15 GHz. Thus, processing a signal with a frequency of about 1.25 GHz pushes the transistors to their limitations. Further, gain control in a conventional receiver circuit adjusts the input signal prior to processing with a phase lock loop. Using CMOS processing, accurately adjusting the gain of the high frequency input data is not presently possible. The economics of IC fabrication create a need for a solution to high speed clock recovery using CMOS technology.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a CMOS receiver circuit capable of recovering a clock signal and data in a high speed data communication system. Further, there is a need for a receiver which can automatically adjust gain to changes in the communication data voltage.
SUMMARY OF THE INVENTION
The above mentioned problems with high speed data communication receiver circuits and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
REFERENCES:
patent: 5015970 (1991-05-01), Williams et al.
patent: 5448598 (1995-09-01), Yousefi et al.
patent: 5483180 (1996-01-01), Chai et al.
patent: 5574756 (1996-11-01), Jeong
patent: 0595632 (1993-10-01), None
patent: 0856946 (1998-08-01), None
Lin, J.Y., et al., “Design of Clock Recovery MMIC using large-signal computer-aided analysis”,Microwave Symp. Degest, IEEE MTT-S Int'l, vol. 3, XP002135220, 1181-1184, (1995).
Wu, L., et al., “A Low Jitter 1.25GHz CMOS analog PLL for clock recovery”,Proceedings of the 1998, IEEE Int'l Symp. of Circuits and Systems, ISCAS '98 vol. 1, XP002135219, 167-170, (May 1998).
Akin, T., “A Wireless Implantable Multichannel Digital Neural Recording System for a Micromachined Sieve Electrode”,IEEE Journal of Solid-State Circuits, 33, 109-118, (Jan. 1998).
Fiedler, A., et al., “A 1.0625Gbps Transceiver with 2x-Oversampling and Transmit Signal Pre-Emphasis”,ISSCC97/Session 15./Serial Data Communications/Paper FP 15.1, IEEE Solid States Circuit Conference, 238, (1997).
Gardner, F.M., “Charge-Pump Phase-Lock Loops”,IEEE Trans. Commun. vol. COM-28, 321-329, (Nov., 1980).
Gardner, F.M., “Phase Accuracy of Charge Pump PLL's”,IEEE Trans. Commun, COM-30, 2362-2363, (Oct. 1982).
Gardner, F.M., “Sequential Phase Detectors”, In: PhaseLock Technologies, Second Edition, John Wiley & Sons, 121-125, 1979.
Gregorian, R., et al., “Switched-Capacitor Circuit Design”,IEEE, 71, 941-966, (Aug. 1983).
Hogge, Jr., C.L., “A Self Correcting Clock Unit”,IEEE Journal of Lightwave Technology, vol. LT-3, 1312-1314, (Dec., 1985).
Meyer, R.G., et al., “Monolithic AGC Loop fpr a 160 Mb/s Transimpedance Amplifier”,IEEE Jornal of Solid-State Circuits, 31, 1331-1335, (Sep. 1996).
Moon, Y., “A 32 x 32-b Adiabatic Register File with Supply CLock Generator”,IEEE Journal of Solid-State Circuits, 33, 696-701, (May 1998).
Nakamura, M., et al., “A 156-Mb/s CMOS Optical Receiver for Burst-Mode Transmission”,IEEE Journal of Solid-State Circuits, 33, 1179-1187, (Aug. 1998).
Petersen, C., et al., “A 3.5VCMOS 32Mb/s Fully-Integrated Read Channel For Disk-Drives”,IEEE Custom Integrated Circuits Conference,vol. 10, Chptr. 2, 1-4, (1993).
Rezzi, F., et al., “A 70-mW Seventh-Order Filter with 7-50 MHz Cutoff Frequency and Programmable Boost and Group Delay Equalization”,IEEE Journal of Solid State Circuits, vol. 32, No. 12, 1987-1999, (Dec. 1997).
Steininger, J.M., “Understanding Wide-band MOS Transistors”,Circuitc and Devices, 27-30, (May 1990).
Su, D.K., et al., “An IC for Linearizing RF Power Amplifiers Using Envelope Elimination and Restoration”,IEEE Journal of Solid State Circuits, 33, 2252-2258, (Dec. 1998).
Chen Yiqin
Grung Bernard L.
Robinson Moises E.
Mis David
Schwegman - Lundberg Woessner - Kluth
Xilinx , Inc.
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