Phase lock loop

Details Phase lock loop Phase lock loop

1988-08-02

1989-10-17

Canney, Vincent P.

Dynamic magnetic information storage or retrieval

General processing of a digital signal

Data clocking

331 1A, G11B 509, H03L 700

Patent

active

048751081

ABSTRACT:
A phase lock loop includes a phase shift apparatus to provide a plurality (i.e., four) phase-shifted clock signals from the VCO. A phase selector is responsive to a triggering signal from a one-shot multivibrator to select the one phase-shifted clock signal next following termination of the trigger signal. The one-shot is responsive to a change between the read and write mode to initiate operation of the phase selector. As a result, the initial phase error between the input signal (read pulses or write clock) and the clock signal of the phase lock loop is no more than 1/8 window.

REFERENCES:
patent: 4005479 (1977-01-01), Hunnicutt et al.
patent: 4376268 (1983-03-01), Moriya et al.
patent: 4577241 (1986-03-01), Wilkinson
patent: 4580176 (1986-04-01), Graves et al.
patent: 4712076 (1987-12-01), Cronch et al.
patent: 4754225 (1988-06-01), Minuhin
Adaptec, Inc., "AIC-6225 High-Performance Monolithic Data Seperator", Copyright 1987, pp. 1-17 and 20-23.
EDN News "Data Seperator Runs at 33M BPS", Aug. 1987, pp. 5 and 15.
Silicon Systems, Inc., Data Book "SSI 32D531 Data Seperator and Write Precompensation Circuit", 6/87, pp. 3-2 thru 3-37.
IBM Technical Disclosure Bulletin, "Phase-Locked Oscillator Charge Pump", vol. 29, No. 2, Jul. 1986, pp. 553-555.

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