Phase lock clock recovery with aided frequency aquisition

Details Phase lock clock recovery with aided frequency aquisition Phase lock clock recovery with aided frequency aquisition

1989-09-01

1990-08-14

Pascal, Robert J.

Oscillators

Automatic frequency stabilization using a phase or frequency...

Plural a.f.s. for a single oscillator

331 34, H03L 700

Patent

active

049490516

ABSTRACT:
In a burst mode fiber-optic transmitter-receiver or bus interface unit (BIU), the clock recovery process by a phase lock loop (PLL), or more generally a servo loop, detects the frequency difference between the PLL oscillator and the transmitter oscillator, and generates a control voltage which is combined with the voltage controlled oscillator (VCO) error voltage to urge the PLL oscillator towards the transmitter's frequency. An activity detector detects the presence of received signal, and "freezes" or holds the control voltage to the PLL so the PLL is free to slew to the frequency and phase of the clock of the received burst. Thus, the PLL is maintained near the expected frequency of the received clock signal for fast acquisition. After the burst, the activity detector once again allows the frequency control signal to assert command of the VCO frequency.

REFERENCES:
patent: 3697690 (1972-10-01), Aaron et al.
patent: 4100503 (1978-07-01), Lindsey et al.
patent: 4101844 (1978-07-01), Malone
patent: 4243941 (1981-01-01), Zdunek
patent: 4556866 (1985-12-01), Gorecki
patent: 4787097 (1988-11-01), Rizzo
"Architecture and Design of a Reliable Token-Ring Network," IEEE J. on Selected Areas in Communications, Nov. 1983, pp. 756-765, by Werner Bux et al.

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