Phase linking of output clock with master clock in memory archit

Details Phase linking of output clock with master clock in memory archit Phase linking of output clock with master clock in memory archit

1996-05-20

1998-09-08

Heckler, Thomas M.

395559, G06F 110

Patent

active

058058737

ABSTRACT:
An independent and cooperative memory architecture is provided which includes a plurality of multi-line channels each capable of carrying either data or address information to a plurality of independent memory clusters. The memory architecture includes a slave port for shifting the burden of scheduling and synchronization from a master device to a memory device. By coupling the master device's clock signal to a counter and to an enabler coupled to a FIFO, the slave port makes it possible for the master device to request data from the memory device and to begin clocking out the requested data from the slave port after a fixed number of clock cycles of the master device's clock. The slave port guarantees that data from the memory device is available to the master device following an output access time of the memory device.

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