Coded data generation or conversion – Converter compensation
Reexamination Certificate
2007-12-11
2007-12-11
Barnie, Rexford (Department: 2819)
Coded data generation or conversion
Converter compensation
C341S120000
Reexamination Certificate
active
11414751
ABSTRACT:
A circuit includes a phase interpolator and a self test circuit. The phase interpolator is to provide a interpolator output having a phase corresponding to a respective phase step in a plurality of phase steps. The interpolator output is a weighted combination of one or more of a plurality of phasor signals. The self test circuit includes a phase detector coupled to a reference signal and the interpolator output, a phase-difference-to-voltage converter coupled to the phase detector, an analog-to-digital converter (ADC) coupled to the phase-difference-to-voltage converter, and control logic. The phase detector is to generate an output that is proportional to a phase difference between the reference signal and the interpolator output. The phase-difference-to-voltage converter is to convert the output from the phase detector into a corresponding voltage. The ADC is to convert an output from the phase-difference-to-voltage converter into a corresponding digital value. The control logic is to test the phase interpolator using the self-test circuit.
REFERENCES:
patent: 6366225 (2002-04-01), Ozdemir
patent: 6438721 (2002-08-01), Wente
patent: 6512473 (2003-01-01), Sasaki
patent: 6816987 (2004-11-01), Olson et al.
patent: 6850051 (2005-02-01), Roberts et al.
patent: 6873939 (2005-03-01), Zerbe et al.
patent: 6889350 (2005-05-01), Fought et al.
patent: 6912665 (2005-06-01), Ellis et al.
patent: 6944692 (2005-09-01), Smith et al.
Chang, K., et al., “Clocking and Circuit Design for a Parallel I/O on a First-Generation CELL Processor,” 2005 IEEE Int'l Solid-State Circuits Conf., Feb. 6-10, 2005, pp. 526-615.
Chang, K., et al., “A 0.4-4 Gb/s CMOS Quad Transceiver Cell Using On-Chip Regulated Dual-Loop PLLs,” IEEE Journal of Solid-State Circuits, vol. 38, No. 5, May 2003, pp. 747-754.
Chang, K., et al., “A 0.4-4 Gb/s CMOS Quad Transceiver Cell Using On-Chip Regulated Dual Loop PLLs,” Symposium on VLSI Circuit Digest of Technical Papers, Jun. 13-15, 2002, pp. 88-91.
Assaderaghi Fariborz
Shi Xudong
Barnie Rexford
Mai Lam T.
Morgan & Lewis & Bockius, LLP
Rambus Inc.
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