Phase latched differential charge pump circuit and method

Oscillators – Automatic frequency stabilization using a phase or frequency... – Particular error voltage control

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331 1A, 331 14, 331 25, 331DIG2, 327157, H03L 7095, H03L 712

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active

056990200

ABSTRACT:
A loop circuit such as a delay lock loop or a phase lock loop includes circuitry for changing the strength of the lock after lock has been achieved. Before lock is achieved, the strength of the charge pump circuitry that controls the charge in the low-pass filter in the loop may be relatively weak. After lock has been achieved, the strength of the charge pump circuit may be increased so that the circuit can maintain its locked condition in a noisy environment.

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patent: 5260611 (1993-11-01), Cliff et al.
U. Ko et al., "A 30-ps Jitter, 3.6-.mu.s Locking, 3.3-Volt Digital PLL For CMOS Gate Arrays", IEEE 1993 Custom Integrated Circuits Conference, pp. 23.3.1-23.3.4.
A. Efendovich et al., "Multi-Frequency Zero-Jitter Delay-Locked Loop", IEEE 1993 Custom Integrated Circuits Conference, pp. 27.1.1-27.1.4.
A. Efendovich et al., "Multifrequency Zero-Jitter Delay-Locked Loop", IEEE Journal of Solid-State Circuits, vol. 29, No. 1, Jan. 1994, pp. 67-70.
A. Walzman, "A Delay Line Loop for Frequency Synthesis of De-Skewed Clock", IEEE International Solid-State Circuits Conference 1994, pp. 298-299.

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