Phase frequency synchronism circuitry and optical receiver

Pulse or digital communications – Receivers

Reexamination Certificate

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Details

C375S375000

Reexamination Certificate

active

07099407

ABSTRACT:
In order to solve the problem that since a loop filter constant suitable for asynchronous state cannot be selected in the conventional phase frequency synchronism circuit, it takes a long time to synchronize the input data and the clock signal from the asynchronous state, the present invention is to propose a phase frequency synchronism circuit including a phase comparator for generating a voltage according to the phase difference of the clock signal to the input signal, a frequency comparator for deciding if the frequency of the clock signal is higher or lower than the transmission rate of the input signal and generating a binary signal, a synchronous identifying unit for deciding if the input signal and the clock signal are synchronized in their phases and frequencies, a first switch that receives the output from the phase comparator and is closed and opened when the synchronous identifying unit decides that they are synchronized and not synchronized, respectively, a second switch that receives the output from the frequency comparator and is opened and closed when the synchronous identifying unit decides that they are synchronized and not synchronized, respectively, a loop filter that receives the outputs from the first and second switches, and a voltage controlled oscillator that oscillates on the basis of the output from the loop filter.

REFERENCES:
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patent: 06-104748 (1994-04-01), None
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patent: 9-284269 (1997-10-01), None
Ansgar Pottbecker, et al., “TP 10.3: A 8Gb/s Si Bipolar Phase and Frequency Detector IC for Clock Extraction,”1992 IEEE International Solid State Circuits Conference(Feb. 20, 1992), Paper 10.3, pp. 162-163

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