Phase frequency detector with programmable minimum pulse width

Details Phase frequency detector with programmable minimum pulse width Phase frequency detector with programmable minimum pulse width

2005-09-20

2005-09-20

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S158000, C327S161000, C327S007000, C327S008000

Reexamination Certificate

active

06946887

ABSTRACT:
A structure and associated method for reducing a static phase error in a phase-locked loop circuit. The phase-locked loop circuit comprises a voltage controlled oscillator and a phase frequency detector. The voltage controlled oscillator is adapted to provide a first clock signal comprising a first frequency. The phase frequency detector is adapted to compare the first clock signal comprising the first frequency to a reference clock signal comprising a reference frequency. The phase frequency detector comprises a programmable circuit adapted to vary a minimum pulse width of an increment pulse and a minimum pulse width of a decrement pulse. The programmable circuit is further adapted to reduce a static phase error of the phase locked-loop circuit.

REFERENCES:
patent: 4970475 (1990-11-01), Gillig
patent: 6049233 (2000-04-01), Shurboff
patent: 6144242 (2000-11-01), Jeong et al.
patent: 6285219 (2001-09-01), Pauls
patent: 6320424 (2001-11-01), Kurd et al.
patent: 6326812 (2001-12-01), Jefferson
patent: 6621320 (2003-09-01), Wong et al.

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