Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By phase
Reexamination Certificate
2001-09-04
2003-07-08
Ton, My-Trang Nu (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific signal discriminating without subsequent control
By phase
Reexamination Certificate
active
06590427
ABSTRACT:
FIELD OF THE INVENTION
This application relates generally to phase lock loop technology and more particularly to a phase detection system for phase lock loop circuits. More particularly still, the present invention relates to a phase detector that reduces dead band.
BACKGROUND OF THE INVENTION
Phase lock loop circuits are prevalently used in many and various technologies. In general, a phase lock loop circuit receives an incoming data signal and analyzes that data signal to generate an output clock signal that is synchronized to the incoming data signal. Creating the synchronized output clock is highly beneficial as this synchronized clock signal can then be used in many different algorithms to further analyze and utilize the incoming data signal in a meaningful manner. For instance, if the incoming data signal must be sampled at a particular point in time in relation to the data signal itself, then it is important to identify the frequency and phase of the incoming data signal to allow for proper sampling of the data signal. Thus, the output clock signal is created with timing characteristics that correspond to the input signal such that the input data signal can be sampled at a meaningful time.
An exemplary phase lock loop system may be a component of a computer disc drive's read channel timing recovery circuit. Phase lock loops are typically used in the disc drive industry to recover the read clock and to generate the write clock at a variety of frequencies depending on which data zones are used.
Phase lock loop circuits typically have a phase detector circuit that receives the data signal and a feedback clock signal. The feedback clock signal is representative, if not identical to the generated output clock signal in terms of phase and frequency. The typical phase detector compares these two input signals, in terms of phase and produces two output control signals “pump up” and “pump down” in response to the comparison. These “pump up” and “pump down” signals are conducted to a charge pump, which, using integration techniques, produces a proportional voltage signal in relation to the received pump up and pump down signals. The voltage signal produced by the charge pump is then conducted to a voltage-controlled oscillator (VCO), which in turn, generates an oscillating voltage clock signal based on the received voltage value. The resulting oscillating signal typically becomes the phase-lock-loop generated clock signal used for future analysis.
A known problem with phase detectors occurs when an input pulse is missing on the data signal. Without added intelligence to handle such a situation, the phase detector, as a result of comparing a pulse with a non-pulse, conducts a signal to the charge pump signifying that the two signals are significantly out of phase, i.e., a pump up or pump down condition. The charge pump reacts to these control signals and remains in a charged state and thus creates an output voltage that may be inappropriate. Prior art solutions to this problem involve using digital logic to test for missing pulses and disable the phase detector during the missing pulse time. Consequently, detecting the missing pulse situation allows the phase detector to modify the signal delivered to the charge pump so that it may “coast” and not substantially impact the output of the VCO during that time frame.
In order to provide a phase detector having integral, missing-pulse-detection logic, the phase detector itself is typically made up of digital logic. Phase detectors that incorporate such digital logic, however, suffer from a unique problem known as “deadband.” That is, as the data signal and the feedback clock signal achieve an “in-phase” condition, wherein each signal has essentially the same phase, and thus should be locked, the resulting control signals from the digital phase detector become very small pulses, e.g., approximately five nanosecond pulses. These very small pulses must turn on the analog components of the charge pump to create a proportional voltage, i.e., a voltage proportional to the pulse width. However, when the pulses are so small, the charge pump may not adequately turn on, due to turn on time of the circuit components associated with the charge pump, e.g., three nanosecond turn on time.
When the charge pump fails to turn on, no output control signal is conducted to the VCO, which may react by forcing the clock signal more out of phase. Consequently, typical digital phase lock loop systems continually force the clock signal from being in a phase lock situation to a non-phase lock situation and then back to a phase lock situation. In other words, as the system becomes closer to being in a locked or optimal condition, the smaller the pulses become and therefore prevent the charge pump from turning on which allows the clock to drift out of phase. As the clock drifts out of phase, the pulses become larger and the charge pump turns on to force the clock back in phase, etc. This situation is also known as jitter wherein the clock signal is continuously forced in and out of a phase lock situation.
In order to better understand the present invention, the following brief discussion of a typical prior-art, digital phase detector is provided.
FIG. 2
illustrates such a digital phase detector circuit
200
, which includes a first flip flop
202
and a second flip flop
204
. Flip flop
202
receives a digital data signal
206
, while flip flop
204
receives the feedback clock signal
208
. The Q outputs of the flip flops
202
and
204
are buffered by buffers
210
and
212
, respectively, and conducted to a charge pump (not shown), as pump up signal
214
and pump down signal
216
, respectively. The charge pump, to produce a control voltage, evaluates the widths of the resulting signals on
210
and
212
.
The “Q” output signals of flip flops
202
and
204
are conducted to NAND gate
218
, which conducts a signal to effectively clear the flip flops
202
and
204
. Due to inherent delays in the various components, such as
202
,
204
and
218
the flip flops
202
and
204
are not cleared immediately following a situation wherein both of the inputs to the NAND gate
218
become high. Consequently, small pulses are still conducted to the charge pump on signals
214
and
216
.
FIG. 3
illustrates sample waveforms relating to the prior-art, phase detector
200
shown in FIG.
2
. As shown, feedback clock signal
208
and data signal
206
relate to digital pulse signals. Also as shown in
FIG. 3
, pump down signal
216
conducts a pulse following the rising edge of the feedback clock signal
208
. The delay
220
between the rising edges of signals
208
and
216
relates to the time delay in the flip flop
204
and buffer
212
. Similarly, the pump up signal
214
conducts a pulse following the rising edge of the data signal
206
. The delay
222
between the rising edges of signals
206
and
214
relates to the propagation time delay in the flip flop
202
and buffer
210
. The difference in phase may be determined by analyzing the difference in the rising edges of the two signals
206
and
208
or, as shown by determining the delay
224
between the rising edges of the two output signals
214
and
216
.
Since the flip flops
202
and
204
are cleared by the NAND gate
218
as soon as the two Q output signals are high, the width of pulse
226
is determined by the delay associated with the NAND gate
218
and delay in clearing the flip flop
202
. This width may be extremely short and thus the pulse width may be very small. Importantly, this small pulse may not be high long enough to turn on the components of the charge pump such that the charge pump does not alter its output in response to the small pulse. Moreover, as shown in
FIG. 3
, as the signals
206
and
208
become more in phase, the width of pulses on
216
become almost as narrow as the pulses on
214
. Consequently, the charge pump may not read any signal from the phase detector which prevents any correction from taking place, which condition is known as a dead band, i.e., when
Murphy Robert Dale
Murray Peter
Merchant & Gould P.C.
Nu Ton My-Trang
Seagate Technology LLC
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