Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
2001-10-16
2003-05-20
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S536000, C327S003000, C327S007000, C327S012000, C331S025000, C363S059000, C363S060000
Reexamination Certificate
active
06566923
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method and/or architecture for phase lock loops generally and, more particularly, to phase-frequency detection and charge pumping with feedback.
BACKGROUND OF THE INVENTION
Referring to
FIG. 1
, a phase-frequency detector
10
and a charge pump
12
for a conventional phase lock loop are shown. The phase-frequency detector
10
comprises two flip-flops
14
and
16
, a logic gate
18
, and a delay circuit
20
. The charge pump
12
comprises a current, source
22
, a current source
24
, a switch, SW_PU, and a switch SW_PD. The charge pump
12
may have an interface
26
to present an output signal (i.e., IOUT).
The flip-flop
14
presents a signal (i.e., PUMP_UP) in response to a rising edge of a reference signal (i.e., REF). The other flip-flop
16
presents a signal (i.e., PUMP_DOWN) in response to an input signal (i.e., IN). The logic gate
18
performs a logical AND function on the signal PUMP_UP and the signal PUMP_DOWN to present a reset signal (i.e., RESET). The delay line
20
delays the signal RESET back to the flip-flops
14
and
16
. The signal PUMP_UP is also presented to the switch SW_PU in the charge pump
12
. The signal PUMP_DOWN is presented to the switch SW_PD in the charge pump
12
. While the signal PUMP_UP is in an active state, the switch SW_PU closes causing a current signal (i.e., I
1
) to flow from the current source
22
to the signal IOUT. While the signal PUMP_DOWN is in active state, the switch SW_PD closes causing a current signal (i.e., I
2
) to flow from the current source
24
to the signal IOUT.
Referring to
FIG. 2
, a timing diagram of the signals shown in
FIG. 1
is provided. The timing diagram shows a scenario where the signal REF transitions low to high before the signal IN. In a scenario where the signal IN transitions low to high before the signal REF then the signal PUMP_DOWN will become active before the signal PUMP_UP thus causing the signal IOUT to have a negative value.
A rising edge
30
in the signal REF will cause a transition
32
in the signal PUMP_UP from an inactive state to an active state. The signal PUMP_UP transition
32
to the active state causes a transition
34
in the signal I
1
from a non-flowing state to a flowing state. The signal I
1
is added to the signal IOUT causing a transition
36
in the signal IOUT to a positive non-zero value.
A rising edge
38
in the signal IN causes a transition
40
in the signal PUMP_DOWN from the inactive state to the active state. The signal PUMP_DOWN transition
40
results in a transition
42
in the signal I
2
from the non-flowing state to the flowing state. The signal I
2
is added to the signal IOUT causing a transition
44
in the signal IOUT back to a zero value. The signal I
1
and the signal I
2
are conventionally designed to be identically opposite currents. As a result, while both the signal I
1
and signal I
2
are flowing, the signal IOUT has the zero value.
The combination of the signal PUMP_UP and the signal PUMP_DOWN in the active state may cause the signal RESET to become active at an output of the logic gate
18
. The delay circuit
20
will delay the signal RESET for a delay period (e.g., MARGIN). At the end of the delay period MARGIN, a transition
46
takes place in the signal RESET from the inactive state to the active state. The signal RESET transition
46
causes a transition
48
in the signal PUMP_UP and a transition
50
in the signal PUMP_DOWN to the inactive state. The signal PUMP_UP in the inactive state causes a transition
52
in the signal I
1
to the non-flowing state. The signal PUMP_DOWN in the inactive state causes a transition
54
in the signal I
2
to the non-flowing state. The signal PUMP_UP and/or the signal PUMP_DOWN in the inactive state causes a transition
56
in the signal RESET to the inactive state.
A duration of the signal PUMP_UP minus a duration of the signal PUMP_DOWN equals a difference in arrival times of edges in the signal REF and the signal IN. The difference in arrival times determines a duration of the signal IOUT at the non-zero value. The delay period MARGIN determines an overlap between the signal I
1
and the signal I
2
.
The purpose of the delay circuit
20
or the delay period MARGIN is to make sure that small phase differences between the signal REF and the signal IN cause the signal I
1
and/or signal I
2
to be switched in the charge pump
12
. If the phase difference between the signal REF and the signal IN is at or near zero, then the switch SW_PU and the switch SW_PD will close approximately simultaneously. Once both the switch SW_PU and the switch SW_PD are closed, the current presented by the upper current source
22
is sinked by the lower current source
24
. Current source
24
sinking the current source
22
establishes the signal IOUT with the zero value.
Without the delay circuit
20
in the phase-frequency detector
10
, a risk is incurred that the signal PUMP_UP and the signal PUMP_DOWN can be too small to cause the switch SW_PU and/or the switch SW_PD to close. Consequently, the phase-frequency detector
10
and the charge pump
12
would not react on very small phase differences between the signal REF and the signal IN.
A problem with the conventional technology is that in order to ensure an overlap in the signal I
1
and the signal I
2
in all situations, the delay circuit
20
must delay the signal RESET for a worst-case situation. The worst-case situation is commonly influenced by process variations, temperature variations, and power supply voltage variations. The worst-case delay may cause several drawbacks. For example, a crowbar current will flow through the charge pump
12
during the delay period MARGIN. Since the delay period MARGIN is longer than required in most situations, an excessive amount of power is consumed.
Another undesirable situation occurs when the signal I
1
and the signal I
2
are not evenly matched. When the signal I
1
and the signal I
2
are not matched, the signal IOUT has a non-zero value during the delay period MARGIN. As a result, the charge pump
12
may present the signal IOUT with a small current that will cause a phase offset in the phase lock loop.
A third situation occurs when the delay period MARGIN is too short. A very short delay period MARGIN commonly results in no overlap between the signal I
1
and the signal I
2
. The non-overlap results in a deadband in the response of the phase lock loop. Slight changes to the phase difference between the signal REF and the signal IN will not result in a change to the signal IOUT.
SUMMARY OF THE INVENTION
The present invention concerns an apparatus comprising a first circuit and a second circuit. The first circuit may be configured to present (i) a pump up signal in response to a reference signal and a reset signal and (ii) a pump down signal in response to an input signal and the reset signal. The second circuit may be configured to (i) switch a pull up signal in response to the pump up signal, (ii) switch a pull down signal in response to the pump down signal, and (iii) present the reset signal in response to switching the pull up signal and the pull down signal.
The objects, features and advantages of the present invention include providing phase-frequency detection and charge pumping with feedback that may (i) detect small phase errors, (ii) reduce current consumption, (iii) minimize crowbar currents, (iv) reduce self-induced phase errors, and/or (v) prevent response deadbands.
REFERENCES:
patent: 5059833 (1991-10-01), Fujii
patent: 5136253 (1992-08-01), Ueno
patent: 5459765 (1995-10-01), Meyer et al.
patent: 5886551 (1999-03-01), Narahara
Callahan Timothy P.
Christopher P. Maiorana P.C.
Cypress Semiconductor Corp.
Ignatowski John J.
Luu An T.
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