Phase error processor

Pulse or digital communications – Repeaters – Testing

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375 82, 375119, 375120, 307511, 328155, 329307, 329309, 329310, 329325, 331 25, 331 1H, H03D 320

Patent

active

052395618

ABSTRACT:
A phase error processor interfaces a proportionate phase detector to a digital loop filter in a high frequency phase-locked loop (PLL). The PLL receives a high frequency stream of NRZI encoded data, which contains a variable density of data signal transitions. A phase detector in the PLL generates proportionate phase error information in the form of a phase error pulse signal PD1 and a reference pulse signal PD2 for each data transition in the incoming data s The phase error processor, using a "decimation" technique, integrates the proportionate phase error information from just one pair of adjacent positive and negative data transitions during each period of N clock cycles if the number of input data transitions which occur during that time period exceeds the expected minimum, otherwise the phase error processor passes no phase error information. The selection of window width is based on the coding scheme of the incoming data stream. The integrated information is converted by the phase error processor once during each N-clock cycle period into a one-bit Up/Down signal that is then used to either advance or retard the output phase of the PLL's digitally controlled oscillator. The phase error processor also detects when the density of edges in the incoming data stream falls below a minimum allowed level, and generates a "data valid" signal indicating whether the Up/Down signal are valid.

REFERENCES:
patent: 4371974 (1983-01-01), Dugan
patent: 4584695 (1986-04-01), Wong et al.
patent: 4635277 (1987-01-01), Blake et al.
patent: 4752748 (1988-06-01), Grzeszykowski
patent: 4940948 (1990-07-01), Laws et al.
patent: 5003557 (1991-03-01), Fujiyama
patent: 5003562 (1991-03-01), van Driest et al.
European Search Report, Application No. EP 9230 6099, dated Sep. 21, 1992.

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