Phase error detector and magnetic storage device using the same

Dynamic magnetic information storage or retrieval – General recording or reproducing – Specifics of equalizing

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360 51, G11B 0509

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active

057453152

ABSTRACT:
In the PRML, the probability of false locking of phase in a metastable state is reduced and the residual phase error between a readout signal and a clock signal used in an A/D conversion is eliminated by a phase detector (10) which comprises a level decision circuit 12 for determining one of a plurality of aimed equalization levels predetermined in the partial response signalling system which is the closest to a sampled value of an equalized waveform equalized substantially to the waveform of the partial response signalling system, a waveform gradient judge circuit (14) for determining a gradient of the equalized waveform on the basis of the aimed equalization level determined by the level decision circuit (12), an equalization error calculation circuit (16) for calculating an equalization error which is a difference between the sampled value of the equalized waveform and the aimed equalization level determined by the level decision circuit (12) and a phase error calculation circuit (18) for detecting a phase error on the basis of the equalization error calculated by the equalization error calculation circuit (16) and the gradient of the equalized waveform determined by the waveform gradient judge circuit (14).

REFERENCES:
patent: 5420884 (1995-05-01), Inove
F. Dolivo et al., "Performance and Sensitivity Analysis of Maximum-Likelihood Sequence Detection on Magnetic Recording Channels", IFEE Transactions on Magnetics, vol. 25, No. 5. Sep 1989, pp. 4072-4074.
F. Dolivo et al., "Fast Timing Recovery for Partial-Response Signaling Systems", International Conference on Communication, Jun. 1989, pp. 0573-0577.

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