Phase error detecting circuit and synchronization clock...

Dynamic information storage or retrieval – Condition indicating – monitoring – or testing – Including radiation storage or retrieval

Reexamination Certificate

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Reexamination Certificate

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10533434

ABSTRACT:
In a phase error detecting circuit used in a synchronous clock extracting circuit for extracting a clock which is synchronized with reproduced data, a cross reference value generator72inputs, as a rising cross reference value S5, rising phase error data S3calculated in a phase error calculator71to a rising cross detector70aand inputs, as a falling cross reference value S6, falling phase error data S4similarly calculated to a falling cross detector70b. Each of the cross detectors70aand70bcalculates a difference value between the value of the reproduced data at a sampling point and the inputted cross reference value (cross offset value) S5or S6and outputs a rising or falling cross detection signal when one of two difference values at consecutive sampling points is negative and the other thereof is positive. Accordingly, a capture range is enlarged.

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patent: 5629914 (1997-05-01), Clark et al.
patent: 5848047 (1998-12-01), Fujimoto
patent: 6151282 (2000-11-01), Hamada et al.
patent: 2002/0181360 (2002-12-01), Hamada et al.
patent: 2000-132921 (2000-05-01), None
patent: 2000-200467 (2000-07-01), None
patent: 2000-243041 (2000-09-01), None

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