Phase error control for phase-locked loops

Details Phase error control for phase-locked loops Phase error control for phase-locked loops

2000-08-18

2002-09-24

Mis, David (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Particular error voltage control

C331S00100A, C331S025000, C327S156000, C327S157000, C327S159000

Reexamination Certificate

active

06456165

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates generally to phase-locked loops and more specifically to phase error control circuitry for phase-locked loops.
2. Related Art
In general, a phase-locked loop (PLL) circuit is a circuit that produces an output signal that is synchronized with an input reference signal. The PLL output signal is synchronized with a reference signal when the frequency and phase of the output signal are the same as that of the reference signal. Should a deviation in the desired phase difference of such signals develop, the PLL will attempt to adjust the frequency and phase of its output signal to drive the phase error toward zero.
There are several different types of PLL devices. Among these are PLL devices that are based on charge pumps. In these PLL devices, a phase comparator compares an input reference signal to an output signal from a voltage controlled oscillator for the purpose of observing phase and frequency differences between the signals. If differences are observed, the phase comparator produces logic pulses indicative of such differences. The charge pump receives these logic pulses and, based thereon, provides pulses of current to a loop filter and to a voltage-controlled, or current-controlled oscillator. As filtered, these current pulses serve to adjust the voltage/current-controlled oscillator to compensate for the observed differences.
Because traditional PLL devices normally use charge pumps with gains optimized for steady state performance parameters such as jitter, a problem may occur if the operating point of the PLL is changed. That is, when one output frequency value is changed to another output frequency value, it takes some time for the circuit to reduce and eliminate the phase error.
Accordingly, a need has developed in the art for a PLL device that will improve the settling time of the device for changes in operating points without producing much overhead in the device.
SUMMARY OF THE INVENTION
The present invention provides a phase-locked loop (PLL) device and system that allows for a quick transition from a first operating point to a second operating point when the phase error exceeds a user-defined threshold. This phase error control is accomplished by adding an additional charge pump and accompanying user-settable circuitry to the PLL device.
Generally, the present invention provides a phase-locked loop device comprising:
a main charge pump;
an auxiliary charge pump; and
a phase error control charge pump that is only active when a phase error of said PLL device exceeds a user-defined value.
In addition, the present invention provides a method for a PLL device to quickly change operating points comprising:
a) providing a phase error control charge pump; and
b) activating said phase error control charge pump only when a phase error of said PLL device exceeds a user-defined value.
The present invention also provides a phase-locked loop system having a PLL device comprising:
a phase comparator, for comparing an input signal with an output signal of said PLL device and determining said phase error with said comparison;
a main charge pump, coupled to said phase comparator;
an auxiliary charge pump, coupled to said phase comparator;
a phase error control charge pump, coupled to said phase comparator, said phase error control charge pump being active only when a phase error of said PLL device exceeds a user-defined value;
an oscillator, coupled to said main charge pump, said auxiliary charge pump and said phase error control charge pump, for outputting said output signal; and
a lock indicator, coupled to said input signal, for indicating when said PLL system is in phase.
The foregoing and other features of the invention will be apparent from the following more particular description of embodiments of the invention, as illustrated in the accompanying drawings.


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