Phase-error-compensation techniques in a fractional-N PLL...

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing

Reexamination Certificate

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C327S156000

Reexamination Certificate

active

06960947

ABSTRACT:
A fractional-type phase-locked loop circuit, for synthesizing an output signal multiplying a frequency of a reference signal by a selected fractional conversion factor, includes a frequency divider for generating a feedback signal dividing the frequency of the output signal by a frequency division factor selectable among at least two different integer-value division factors, and frequency divider control means for causing the frequency division factor to vary between the at least two integer-value division factors in a pre-defined number of cycles, thereby an average frequency division factor over said pre-defined number of cycles has a fractional value. Means are provided for compensating a phase error introduced by the frequency divider on the basis of a value indicative of the phase error obtained from said frequency divider control means. The phase-error compensation means includes rounding means, receiving an input binary code with a first number of binary digits, indicative of the phase error value, and providing an output binary code, with a second number of binary digits lower than the first number of digits, defining a rounded phase error value.

REFERENCES:
patent: 3959737 (1976-05-01), Tanis
patent: 4492936 (1985-01-01), Albarello et al.
patent: 5708687 (1998-01-01), Powell et al.
patent: 6236275 (2001-05-01), Dent
patent: 6236703 (2001-05-01), Riley
patent: 10105057 (2002-08-01), None
patent: 2097206 (1982-10-01), None
European Search Report dated Sep. 1, 2003 relating to the above prior art.

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