Phase error cancellation

Details Phase error cancellation Phase error cancellation

2006-06-27

2006-06-27

Callahan, Timothy P. (Department: 2816)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Particular error voltage control

C327S147000, C327S156000

Reexamination Certificate

active

07068110

ABSTRACT:
A noise cancellation signal is generated for a fractional-N phase-locked loop by supplying a divide value to a first delta sigma modulator and generating a divide control signal in a first delta sigma modulator to control a divide value of a feedback divider in the phase-locked loop. The first delta sigma modulator integrates an error term indicative of a difference between a value of the generated divide control signal and the divide value supplied to the first delta sigma modulator. A phase error cancellation signal is generated by quantizing the integrated error term using a second delta sigma modulator. The error term can be used by the second delta sigma modulator while quantizing the integrated error term, thereby limiting the low pass filter effects of the second delta sigma modulator in the cancellation signal.

REFERENCES:
patent: 5038117 (1991-08-01), Miller
patent: 5337024 (1994-08-01), Collins
patent: 5604468 (1997-02-01), Gillig
patent: 5781044 (1998-07-01), Riley et al.
patent: 5790614 (1998-08-01), Powell
patent: 5834987 (1998-11-01), Dent
patent: 5847611 (1998-12-01), Hirata
patent: 6008703 (1999-12-01), Perrott et al.
patent: 6044124 (2000-03-01), Monahan et al.
patent: 6236703 (2001-05-01), Riley
patent: 6404246 (2002-06-01), Estakhri et al.
patent: 6456164 (2002-09-01), Fan
patent: 6509800 (2003-01-01), Stockton
patent: 6570453 (2003-05-01), Su et al.
patent: 6670854 (2003-12-01), Takeda et al.
patent: 6917317 (2005-07-01), Nagaso et al.
patent: 2002/0140512 (2002-10-01), Stockton
patent: 1 345 375 (2003-09-01), None
De Muer, Bram, and Steyaert, Michel S. J., “A CMOS Monolithic ΔΣ-Controlled Fractional-N Frequency Synthesizer for DCS-1800,” IEEE Journal of Solid-State Circuits, vol. 37, No. 7, Jul. 2002, pp. 835-844.
Pamarti, Sudhakar, et al., “A Wideband 2,4-GHz Delta-Sigma Fractional-N PLL With 1-Mb/s In-Loop Modulation,” IEEE Journal of Solid-State Circuits, vol. 39, No. 1, Jan. 2004, pp. 49-62.
Riley, Tom A. D., et al., “Delta-Sigma Modulation in Fractional-N Frequency Synthesis,” IEEE Journal of Solid-State Circuits, vol. 28, No. 5, May 1993, pp. 553-559.
Perrott, Michael H., et al., “A 27-mW CMOS Fractional-N Synthesizer Using Digital Compensation for 2.5-Mb/s GFSK Modulation,” IEEE Journal of Solid-State Circuits, vol. 32, No. 12, Dec. 1997, pp. 2048-2060.
Sumi, Yasuaki, et al., “Novel Fractional-N PLL Frequency Synthesizer with Reduced Phase Error,” Proceedings of IEEE Asia Pacific Conference on Circuits and Systems '96, Nov. 18-21, 1996, Seoul, Korea, pp. 45-48.

Affiliated with

Also associated with

Rating

Phase error cancellation does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Phase error cancellation, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Phase error cancellation will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3709382