Phase enable and clock generation circuit

Details Phase enable and clock generation circuit Phase enable and clock generation circuit

1997-06-20

2000-08-08

Le, Dinh T.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

327 99, 327164, H04L 700

Patent

active

061007323

ABSTRACT:
A phase-enable circuit clocks a first functional unit at a first frequency and a second functional unit at a second frequency. Each of the first and second functional units is provided with a first clock signal of the first frequency. A phase-enable generator then uses the first clock signal and a second clock signal of a second frequency lower than the first frequency to develop a phase-enable signal that periodically disables a clock input terminal of the second functional unit so that the second functional unit is clocked at the second frequency. Changing the frequency of the second clock to zero switches the phase-enable circuit into another mode of operation. In that mode, the clock input terminal of the second functional unit is constantly enabled and the first and second functional units are each clocked at the first frequency.

REFERENCES:
patent: 5475324 (1995-12-01), Tomiyori
patent: 5654988 (1997-08-01), Heyward et al.
patent: 5760609 (1998-06-01), Sharpe-Geisler

Affiliated with

Also associated with

Rating

Phase enable and clock generation circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Phase enable and clock generation circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Phase enable and clock generation circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1153716