Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
2000-02-25
2002-01-15
Lam, Tuan (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S147000, C327S153000
Reexamination Certificate
active
06339350
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a phase difference—current conversion circuit used for a PLL circuit or the like.
2. Description of the Related Art
FIG. 10
is a circuit diagram showing a conventional phase difference—current conversion circuit. Hereinafter, a description will be made with reference to this drawing.
The conventional phase difference—current conversion circuit includes a phase comparator
50
for outputting a digital signal corresponding to a phase difference of two signals, a charge pump circuit
54
for outputting a current as an analog signal corresponding to the digital signal outputted from the phase comparator
50
, and a reset circuit
52
as a delay circuit for resetting the digital signal outputted from the phase comparator
50
after a definite delay time in the case where the phases of the two signals have coincided with each other.
The phase comparator
50
is a general digital phase comparator constituted by NAND gates
501
and
508
, and inverters
509
and
510
. In the case where the phases of input signals from terminals Sig and Ref do not coincide with each other, one of terminals Up and Down becomes an H level and the other becomes an L level. In the case where the phases of the input signals from the terminals Sig and Ref coincide with each other, both the terminals Up and Down become the H level first, and become the L level after the definite delay time.
The charge pump circuit
54
is a current mirror circuit constituted by transistors M
5
to M
8
, current sources
541
and
542
, electric switches SW
2
and SW
3
, and the like. In the case where the terminals Up and Up
1
are in the H level, and the terminals Down and Down
1
are in the L level, the electric switch SW
2
is turned off, and the electric switch SW
3
is turned on, so that a current Iup flows out from a terminal CPOUT. On the contrary, in the case where the terminals Up and Up
1
are in the L level, and the terminals Down and Down
1
are in the H level, the electric switch SW
2
is turned on and the electric switch SW
3
are turned off, so that a current Idown flows in from the terminal CPOUT. In the case where both the terminals Up and Up
1
and the terminals Down and Down
1
are in the H level, both the electric switches SW
2
and SW
3
are turned on, so that the current Idown and the current Iup cancel out each other, and a slight difference between those currents is outputted from the terminal CPOUT. On the contrary, in the case where both the terminals Up and Up
1
and the terminals Down and Down
1
are in the L level, since both the electric switches SW
2
and SW
3
are turned off, nothing is outputted from the terminal CPOUT.
The reset circuit
52
is constituted by 2n inverters
521
to 52n connected in series. Conventionally, the number of stages of the inverters
521
, . . . or the size of transistors constituting the inverters
521
, . . . are adjusted, so that the delay time is adjusted.
A delay time of the reset circuit
52
is set so that the time is equal to a rising delay time of the output current of the charge pump circuit
54
. At this time, even in the lock state of PLL in which the input signals from the terminals Sig and Ref of the phase comparator
50
come to have the same phase, the charge pump circuit
54
responds to a very slight phase difference of the input signals from the terminals Sig and Ref, and comes to output a current in proportion to the phase difference. By this, it is possible to avoid a state generally called a dead band in which output current is not in proportion to a phase difference.
Next, problems of the conventional technique will be described.
A first problem is as follows: At the time of PLL lock, a current flowing through the transistor of the output stage of the charge pump is required to have such characteristics that it is cut off after reaching a previously set current value. However, by change of operation conditions of fluctuation of conditions at the time of manufacture, it has not been able to keep the characteristics. This has caused deterioration of noise characteristics.
The reason why the first problem occurs will be described. The delay time of the reset circuit is determined by the gate capacitance of a PMOS transistor and an NMOS transistor constituting an inverter, and the on resistance of a PMOS transistor of the upstream stage inverter. On the contrary, the current rising delay time of the charge pump circuit is determined by a reference current value of the current mirror circuit and gate capacitance of a transistor constituting the current mirror circuit. That is, since the principle based on which the current rising delay time is generated is different between the reset circuit and the charge pump circuit, when power supply voltage, ambient temperature, manufacturing conditions, and the like are changed, the delay time of the reset circuit and the current rising delay time of the charge pump circuit are changed independently from each other. Thus, it has not been able to keep such characteristics that the current flowing through the transistor of the charge pump output stage at the time of PLL lock is cut off after reaching a set current value.
A second problem is as follows: The inverter used as a delay element in the reset circuit has a delay amount per stage for smaller than the current rising delay time of the charge pump circuit. Thus, since several tens stages become necessary for the number of stages of the inverters, it is difficult to set a time in which a charge pump output current at the PLL lock flows, to the optimum length.
The reason why the second problem occurs will be described. When the output current of the charge pump circuit is tried to be set large so as to increase the suppression effect of noise generated in the charge pump circuit, it is necessary to increase the channel width W of a transistor at the output stage. By this, since the gate capacitance of the transistor is increased, the current rising delay time of the charge pump circuit becomes large. On the other hand, in order to cause the reset circuit to generate this delay time, the inverters of several tens stages become necessary. However, it is difficult to form such inverters of several tens stages on a semiconductor chip since a space is not sufficient. As a result, it becomes difficult to keep the time in which the charge pump output current flows at the time of PLL lock, to the optimum length.
SUMMARY OF THE INVENTION
An object of the present invention is therefore to provide a phase difference—current conversion circuit which can always realize such characteristics that a current flowing through a transistor at a charge pump output stage reaches a set value at the time of PLL lock and is cut off, without increasing an occupied area on a semiconductor chip.
A phase difference—current conversion circuit according to the present invention includes a phase comparator for outputting first and second digital signals one of which has a first level and the other of which has a second level in a case where phases of two input signals do not coincide with each other, and for outputting the first and second digital signals both of which have the first level in a case where the phases of the two input signals coincide with each other; a charge pump circuit for outputting an outflow current only when the first digital signal outputted from the phase comparator is in the first level, and outputting an inflow current only when the second digital signal outputted from the phase comparator is in the first level; and a delay circuit for causing the first and second digital signal outputted from the phase comparator to become the second level after a definite delay time in a case where the phases of the two input signals coincide with each other. The charge pump circuit is provided with a current outputting transistor for gently outputting the outflow current or the inflow current by its rising delay time. The delay circuit is provided with a delay time determining transistor
Foley & Lardner
Lam Tuan
Nguyen Hiep
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